POWER MANAGEMENT INTEGRATED CIRCUIT INTEGRATING FIELD EFFECT TRANSISTORS AND PROGRAMMABLE FABRIC

• US 20170115717A1
• Filed: 10/27/2016
• Published: 04/27/2017
• Est. Priority Date: 10/27/2015
• Status: Active Grant

• Current Assignee: Andapt Holdings Limited
• Original Assignee: Lnc. Andapt
• Inventors: SHANKAR, Kapil, CHAN, Thomas, CROTTY, Patrick J., BIRKNER, John
• Granted Patent: US 10,447,276 B2
• Time in Patent Office: Days
• CPC Class Codes: G05F 1/66 Regulating electric power
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17772 for powering on or off
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A power management integrated circuit (PMIC) includes: a plurality of high voltage power field effect transistors (FETs); and a programmable fabric configured to programmably connect one or more of the plurality of high voltage power FETs to provide one or more high power voltage outputs. The plurality of high voltage power FETs and the programmable fabric are integrated in a single chip.

Claims

1. A power management integrated circuit (PMIC) comprising:

a plurality of high voltage power field effect transistors (FETs); and

a programmable fabric configured to programmably connect one or more of the plurality of high voltage power FETs to provide one or more high power voltage outputs,

wherein the plurality of high voltage power FETs and the programmable fabric are integrated in a single chip.

2. The PMIC of claim 1, further comprising a plurality of adaptive blocks and a plurality of input/output (I/O) blocks.

3. The PMIC of claim 2, wherein the plurality of adaptive blocks comprises one or more of an analog-to-digital converter (ADC) block, a memory block, a pulse-width modulation (PWM) block, a voltage reference block, and a timer block.

4. The PMIC of claim 2, wherein the I/O blocks include a drain pad and a source pad of the plurality of high voltage power FETs that are connected to an external electric element or device.

5. The PMIC of claim 2, wherein the I/O blocks provide an external interface of the PMIC.

6. The PMIC of claim 2, wherein the one or more high power voltage outputs provide a plurality of configurable power supply voltages with programmable operating characteristics by programming operating characteristics and connections of the one or more high voltage power FETs, the plurality of adaptive blocks, and the plurality of I/O blocks via the programmable fabric.

7. The PMIC of claim 6, wherein the programmable operating characteristics include one or more of a voltage level, a turn-on sequence, a turn-off sequence, a single-phase operation, a multi-phase operation, a voltage ramp-up, a voltage ramp-down, a voltage tracking, a voltage positioning, a protection mode threshold, a fault detection, and a fault response.

8. The PMIC of claim 1, wherein the plurality of adaptive blocks comprises one or more of a sensor block, a comparator, an analog-to-digital component, a digital-to-analog component, and a voltage reference.

9. The PMIC of claim 1, wherein the programmable fabric includes a plurality of logic elements and a plurality of routing channels.

10. The PMIC of claim 9, wherein the plurality of logic elements includes one or more of memory blocks including a static random-access memory (SRAM), and a non-volatile memory, look up tables, flip flops, and logic gates.

11. The PMIC of claim 1, wherein each of the plurality of high voltage power FETs is capable of handling a voltage ranging from 12V to 80V and current up to 12 A.

12. The PMIC of claim 1, wherein the one or more high power voltage outputs provide one or more functions of a voltage mode buck switching converter, a current mode buck switching converter, a boost regulator, a buck-boost regulator, a low drop-out (LDO) regulator, a load switch, a mux, a battery charger, an external switching controller, a gate driver, and an integrator.

13. The PMIC of claim 1, the plurality of high voltage power FETs includes a DMOS high voltage power FET integrated to a CMOS circuit.