TECHNIQUES FOR ENTRY TO A LOWER POWER STATE FOR A MEMORY DEVICE

• US 20170115916A1
• Filed: 11/07/2016
• Published: 04/27/2017
• Est. Priority Date: 09/23/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jayachandran, Sowmiya, Sundaram, Rajesh, Faber, Robert
• Granted Patent: US 9,916,104 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.

Claims

1. An apparatus comprising:

a plurality of memory cells arranged to complete one or more operations responsive to a command received via a command bus;

one or more first programmable counters maintained with the plurality of memory cells; and

an interface to the one or more first programmable counters to enable a first count value to be programmed to one or more of the first programmable counters, the first count value to set a first delay for the plurality of memory cells to transition from an idle power state to a first low power state after completion of the one or more operations, the first low power state to cause the plurality of memory cells to consume less power compared to the idle power state.

2. The apparatus of claim 1, the command comprises one of a read command or a write command.

3. The apparatus of claim 2, when the command is the write command, the one or more first programmable counters comprises a wait-after-write counter to count down or count up based on the first count value after a write operation is completed by the plurality of memory cells responsive to the write command.

4. The apparatus of claim 2, when the command is the read command, the one or more first programmable counters comprises a wait-after-read counter to count down or count up based on the first count value after a read operation is completed by the plurality of memory cells responsive to the read command.

5. The apparatus of claim 1, the interface to the one or more programmable counters comprises the interface to a plurality of registers maintained with the plurality of memory cells, the plurality of registers accessible to a memory device controller through the interface, the first count value programmed to one or more of the first programmable counters based on the memory device controller able to store the first count value to at least some of the plurality of registers.

6. The apparatus of claim 1, comprises a memory die arranged to be included with a plurality of other memory dies in a solid state drive, the memory die and the plurality of other memory dies to receive commands from a memory device controller via the command bus.

7. The apparatus of claim 1, comprises the one or more first programmable counters to be stopped responsive to a second command received via the command bus before the first delay has expired, the plurality of memory cells to transition from the idle power state to an active power state after the one or more first programmable counters have been stopped, the active power state to cause the plurality of memory cells to consume more power compared to the idle power state.

8. The apparatus of claim 1, comprising:

one or more second programmable counters maintained with the plurality of memory cells; and

the interface to enable a second count value to be programmed to one or more of the second programmable counters, the second count value to set a second delay for the plurality of memory cells to transition from the first low power state to a second low power state after expiration of the of the one or more first programmable counters, the second low power state to cause the plurality of memory cells to consume less power compared to the first low power state.

9. The apparatus of claim 8, comprising the one or more second programmable counters to be stopped responsive to a second command received via the command bus before the second delay has expired, the plurality of memory cells to transition from the second low power state to an active power state after the one or more second programmable counters have been stopped, the active power state to cause the plurality of memory cells to consume more power compared to the idle power state.

10. The apparatus of claim 1, the plurality of memory cells include one or more types of memory to include 3-dimensional cross-point memory, flash memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory, nanowire, ferroelectric transistor random access memory (FeTRAM or FeRAM), nanowire, electrically erasable programmable read-only memory (EEPROM) or dynamic random access memory (DRAM).

11. A method comprising:

receiving, at a memory device, a command for the memory device to complete one or more operations;

starting a first counter having a first count value following completion of the one or more operations, the first counter maintained at the memory device; and

causing the memory device to transition from an idle power state to a first low power state responsive to the first counter expiring, the first low power state to result in the memory device consuming less power compared to the idle power state.

12. The method of claim 11, comprising:

receiving a second command before the first counter has expired;

stopping the first counter based on receiving the second command; and

causing the memory device to transition from the idle power state to an active power state, the active power state to result in the memory device consuming more power compared to the idle power state.

13. The method of claim 11, comprising:

programming the first counter to have the first count value responsive to receiving the first count value from a memory device controller.

14. The method of claim 11, the memory device comprising one of a plurality of memory dies included in a solid state drive, the plurality of memory dies capable of receiving commands from a memory device controller through at least one command bus.

15. The method of claim 11, comprising:

starting a second counter having a second count value following expiration of the first counter, the second counter maintained at the memory device; and

causing the memory device to transition from the first low power state to a second low power state responsive to the second counter expiring, the second low power state to result in the memory device consuming less power compared to the first low power state.

16. The method of claim 15, comprising:

receiving a second command before the second counter has expired;

stopping the second counter based on receiving the second command; and

causing the memory device to transition from the first low power state to an active power state, the active power state to result in the memory device consuming more power compared to the idle power state.

17. The method of claim 15, comprising:

programming the second counter to have the second count value responsive to receiving the second count value from a memory device controller.

18. A system comprising:

at least one command bus; and

a plurality of memory dies coupled with the at least one command bus, the plurality of memory dies to separately include;

a plurality of memory cells arranged to complete one or more operations responsive to a command via the at least one command bus;

one or more first programmable counters; and

an interface to the one or more first programmable counters to enable a first count value to be programmed to one or more of the first programmable counters, the first count value to set a first delay for the plurality of memory cells to transition from an idle power state to a first low power state after completion of the one or more operations, the first low power state to cause the plurality of memory cells to consume less power compared to the idle power state.

19. The system of claim 18, the command comprises one of a read command or a write command.

20. The system of claim 19, when the command is the write command, the one or more first programmable counters comprises a wait-after-write counter to count down or count up based on the first count value after a write operation is completed by the plurality of memory cells at a given memory die from among the plurality of memory dies responsive to the write command that is addressed to the given memory die.

21. The system of claim 19, when the command is the read command, the one or more first programmable counters comprises a wait-after-read counter to count down or count up based on the first count value after a read operation is completed by the plurality of memory cells at a given memory die from among the plurality of memory dies responsive to the read command that is addressed to the given memory die.

22. The system of claim 18, the interface to the one or more programmable counters comprises the interface to a plurality of registers separately maintained by respective memory dies of the plurality of memory dies, the plurality of registers accessible to a memory controller through the interface, the first count value programmed to one or more of the first programmable counters based on the memory controller able to store the first count value to the plurality of registers.

23. The system of claim 18, comprise the one or more first programmable counters to be stopped responsive to a second command via the at least one command bus before the first delay has expired, a given memory die that received the first and second commands to transition the given memory die'"'"'s plurality of memory cells from the idle power state to an active power state after the one or more first programmable counters have been stopped, the active power state to cause the given memory die'"'"'s plurality of memory cells to consume more power compared to the idle power state.

24. The system of claim 18, comprises the plurality of memory dies to also separately include:

one or more second programmable counters; and

the interface to enable a second count value to be programmed to one or more of the second programmable counters, the second count value to set a second delay for the plurality of memory cells to transition from the first low power state to a second low power state after expiration of the one or more first programmable counters, the second low power state to cause the plurality of memory cells to consume less power compared to the first low power state.

25. The system of claim 24, comprising the one or more second programmable counters to be stopped responsive to a second command received via the at least one command bus before the second delay has expired, a given memory die that received the first and second commands to transition the given memory die'"'"'s plurality of memory cells from the second low power state to an active power state after the one or more second programmable counters have been stopped, the active power state to cause the given memory die'"'"'s plurality of memory cells to consume more power compared to the idle power state.

26. The system of claim 18, comprising:

a memory controller coupled with the at least one command bus;

a processor for a computing platform, the processor coupled with the memory controller; and

a network interface for the computing platform, the network interface coupled with the processor and the memory controller.

27. The system of claim 26, comprising a digital display coupled with the processor to present a user interface view.