RADIO FREQUENCY FRONT END DEVICES WITH MASKED WRITE

• US 20170116141A1
• Filed: 10/19/2016
• Published: 04/27/2017
• Est. Priority Date: 10/23/2015
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Mishra, Lalan Jee, Wietfeldt, Richard, O'Shea, Helena Deirdre, Roethig, Wolfgang, Chen, Zhenqi
• Application Number:
  US15/298,071
• Publication Number:
  US 20170116141A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Methods and apparatuses are described that facilitate the communication of data between a transmitter and a receiver across a serial bus interface. In one configuration, a transmitter generates a datagram based on a 16-bit address and a mask-and-data pair burst length, the 16-bit address including a most significant byte (MSB) and a least significant byte (LSB), compares the MSB to a receiver base address maintained in a shadow register, compares the mask-and-data pair burst length to a receiver masked-write burst length maintained in the shadow register, and sends the datagram to the receiver via the bus interface when: the MSB is equal to the receiver base address maintained in the shadow register, and the mask-and-data pair burst length is equal to the receiver masked-write burst length maintained in the shadow register.

Claims

1. A method performed at a transmitter for sending data to a receiver via a bus interface, comprising:

generating a datagram based on a 16-bit address and a mask-and-data pair burst length, the 16-bit address including a most significant byte (MSB) and a least significant byte (LSB);

comparing the MSB to a receiver base address maintained in a shadow register;

comparing the mask-and-data pair burst length to a receiver masked-write burst length maintained in the shadow register; and

sending the datagram to the receiver via the bus interface when;

the MSB is equal to the receiver base address maintained in the shadow register, and

the mask-and-data pair burst length is equal to the receiver masked-write burst length maintained in the shadow register.

2. The method of claim 1, wherein the datagram sent to the receiver does not include the MSB and the mask-and-data pair burst length.

3. The method of claim 1, wherein the comparing the MSB to the receiver base address maintained in the shadow register includes:

detecting whether the MSB is equal to the receiver base address maintained in the shadow register; and

when the MSB is not equal to the receiver base address maintained in the shadow register;

setting a base address at the receiver to be equal to the MSB; and

updating the receiver base address maintained in the shadow register to the MSB.

4. The method of claim 3, wherein the base address at the receiver is set by sending a write access command to the receiver prior to sending the datagram.

5. The method of claim 1, wherein the comparing the mask-and-data pair burst length to the receiver masked-write burst length maintained in the shadow register includes:

detecting whether the mask-and-data pair burst length is equal to the receiver masked-write burst length maintained in the shadow register; and

when the mask-and-data pair burst length is not equal to the receiver masked-write burst length maintained in the shadow register;

setting a masked-write burst length at the receiver to be equal to the mask-and-data pair burst length, and

updating the receiver masked-write burst length maintained in the shadow register to the mask-and-data pair burst length.

6. The method of claim 5, wherein the masked-write burst length at the receiver is set by sending a write access command to the receiver prior to sending the datagram.

7. A transmitter for sending data to a receiver, comprising:

a bus interface; and

a processing circuit configured to;

generate a datagram based on a 16-bit address and a mask-and-data pair burst length, the 16-bit address including a most significant byte (MSB) and a least significant byte (LSB);

compare the MSB to a receiver base address maintained in a shadow register;

compare the mask-and-data pair burst length to a receiver masked-write burst length maintained in the shadow register; and

send the datagram to a receiver via the bus interface when;

the MSB is equal to the receiver base address maintained in the shadow register, and

the mask-and-data pair burst length is equal to the receiver masked-write burst length maintained in the shadow register.

8. The transmitter of claim 7, wherein the datagram sent to the receiver does not include the MSB and the mask-and-data pair burst length.

9. The transmitter of claim 7, wherein the processing circuit is configured to compare the MSB to the receiver base address maintained in the shadow register by:

detecting whether the MSB is equal to the receiver base address maintained in the shadow register; and

when the MSB is not equal to the receiver base address maintained in the shadow register;

setting a base address at the receiver to be equal to the MSB; and

updating the receiver base address maintained in the shadow register to the MSB.

10. The transmitter of claim 9, wherein the processing circuit is configured to set the base address at the receiver by sending a write access command to the receiver prior to sending the datagram.

11. The transmitter of claim 7, wherein the processing circuit is configured to compare the mask-and-data pair burst length to the receiver masked-write burst length maintained in the shadow register by:

detecting whether the mask-and-data pair burst length is equal to the receiver masked-write burst length maintained in the shadow register; and

when the mask-and-data pair burst length is not equal to the receiver masked-write burst length maintained in the shadow register;

setting a masked-write burst length at the receiver to be equal to the mask-and-data pair burst length, and

updating the receiver masked-write burst length maintained in the shadow register to the mask-and-data pair burst length.

12. The transmitter of claim 11, wherein the processing circuit is configured to set the masked-write burst length at the receiver by sending a write access command to the receiver prior to sending the datagram.

13. A method performed at a transmitter for sending data to a receiver, comprising:

generating a mask field in a datagram to be transmitted through an interface to the receiver, the mask field identifying at least one bit to be changed in a radio frequency front end (RFFE) register;

generating a data field in the datagram, the data field providing a value of the at least one bit to be changed in the RFFE register; and

transmitting the datagram through the interface, wherein the datagram is addressed to the RFFE register of the receiver.

14. The method of claim 13, wherein the mask field further indicates a remaining set of bits to be left unchanged in the RFFE register.

15. The method of claim 13, further comprising generating a command field in the datagram, the command field indicating whether the datagram is an extended register masked write command, an extended register long masked write command, a register masked write command, or an extended register short masked write command.

16. The method of claim 13, further comprising:

generating a command field in the datagram, the command field indicating that the datagram is a masked write command; and

generating a mode field in the datagram, the mode field indicating whether the datagram is an extended register masked write command, an extended register long masked write command, a register masked write command, or an extended register short masked write command.

17. The method of claim 13, wherein:

the mask field is a bit index field identifying a bit position to be changed in the RFFE register of the receiver; and

the data field is a bit value field providing a bit value for the bit position identified in the bit index field.

18. A transmitter for sending data to a receiver, comprising:

a bus interface; and

a processing circuit configured to;

generate a mask field in a datagram to be transmitted through the bus interface to the receiver, the mask field identifying at least one bit to be changed in a radio frequency front end (RFFE) register,

generate a data field in the datagram, the data field providing a value of the at least one bit to be changed in the RFFE register, and

transmit the datagram through the bus interface, wherein the datagram is addressed to the RFFE register of the receiver.

19. A method performed at a receiver for receiving data from a transmitter, comprising:

receiving a datagram through an interface from the transmitter, wherein the datagram is addressed to a radio frequency front end (RFFE) register of the receiver;

reading a mask field in the datagram, the mask field identifying at least one bit to be changed in the RFFE register;

reading a data field in the datagram, the data field providing a value of the at least one bit to be changed in the RFFE register; and

changing the at least one bit in the RFFE register identified in the mask field according to the value provided in the data field.

20. The method of claim 19, wherein the mask field further indicates a remaining set of bits to be left unchanged in the RFFE register.

21. The method of claim 19, further comprising reading a command field in the datagram, the command field indicating whether the datagram is an extended register masked write command, an extended register long masked write command, a register masked write command, or an extended register short masked write command.

22. The method of claim 19, further comprising:

reading a command field in the datagram, the command field indicating that the datagram is a masked write command; and

reading a mode field in the datagram, the mode field indicating whether the datagram is an extended register masked write command, an extended register long masked write command, a register masked write command, or an extended register short masked write command.

23. The method of claim 19, wherein:

the mask field is a bit index field identifying a bit position to be changed in the RFFE register of the receiver; and

the data field is a bit value field providing a bit value for the bit position identified in the bit index field.

24. A receiver for receiving data from a transmitter, comprising:

a bus interface; and

a processing circuit configured to;

receive a datagram through the bus interface from the transmitter, wherein the datagram is addressed to a radio frequency front end (RFFE) register of the receiver,

read a mask field in the datagram, the mask field identifying at least one bit to be changed in the RFFE register,

read a data field in the datagram, the data field providing a value of the at least one bit to be changed in the RFFE register, and

change the at least one bit in the RFFE register identified in the mask field according to the value provided in the data field.

25. A method performed at a transmitter for sending data to a receiver through a bus interface, comprising:

enabling a masked-write operation by setting a single bit within a configuration register at the receiver to a first value;

generating a datagram to be transmitted to the receiver via the bus interface, the datagram providing an address value;

generating a payload field in the datagram, the payload field including a number of mask-and-data pairs when the masked-write operation is enabled, wherein each mask-and-data pair includes a mask field identifying at least one bit to be changed in a radio frequency front end (RFFE) register and a data field providing a value of the at least one bit to be changed in the RFFE register; and

transmitting the datagram through the bus interface, wherein the datagram is addressed to the RFFE register of the receiver.

26. The method of claim 25, further comprising:

disabling the masked-write operation by setting the single bit within the configuration register at the receiver to a second value.

27. The method of claim 25, further comprising:

enabling a page segmented access operation by setting another single bit within the configuration register at the receiver to a first value, wherein an address of the RFFE register is a combination of an address value located at a page address register at the receiver and the address value provided by the datagram when the page segmented access operation is enabled; and

disabling the page segmented access operation by setting the other single bit within the configuration register at the receiver to a second value, wherein the address of the RFFE register is the address value provided by the datagram when the page segmented access operation is disabled.

28. A transmitter for sending data to a receiver, comprising:

a bus interface; and

a processing circuit configured to;

enable a masked-write operation by setting a single bit within a configuration register at the receiver to a first value,

generate a datagram to be transmitted to the receiver via the bus interface, the datagram providing an address value,

generate a payload field in the datagram, the payload field including a number of mask-and-data pairs when the masked-write operation is enabled, wherein each mask-and-data pair includes a mask field identifying at least one bit to be changed in a radio frequency front end (RFFE) register and a data field providing a value of the at least one bit to be changed in the RFFE register, and

transmitting the datagram through the bus interface, wherein the datagram is addressed to the RFFE register of the receiver.

29. The transmitter of claim 28, the processing circuit further configured to:

disable the masked-write operation by setting the single bit within the configuration register at the receiver to a second value.

30. The transmitter of claim 28, the processing circuit further configured to:

enable a page segmented access operation by setting another single bit within the configuration register at the receiver to a first value, wherein an address of the RFFE register is a combination of an address value located at a page address register at the receiver and the address value provided by the datagram when the page segmented access operation is enabled; and

disable the page segmented access operation by setting the other single bit within the configuration register at the receiver to a second value, wherein the address of the RFFE register is the address value provided by the datagram when the page segmented access operation is disabled.

31. A method performed at a receiver for receiving data from a transmitter through a bus interface, comprising:

receiving a first datagram from the transmitter for setting a single bit within a configuration register at the receiver;

detecting that a masked-write operation is enabled when the single bit within the configuration register is set to a first value;

receiving a second datagram from the transmitter, the second datagram providing an address value;

reading a payload field in the second datagram, the payload field including a number of mask-and-data pairs when the masked-write operation is enabled, wherein each mask-and-data pair includes a mask field identifying at least one bit to be changed in a radio frequency front end (RFFE) register of the receiver and a data field providing a value of the at least one bit to be changed in the RFFE register; and

changing the at least one bit in the RFFE register identified in the mask field according to the value provided in the data field for each mask-and-data pair.

32. The method of claim 31, further comprising:

detecting that the masked-write operation is disabled when the single bit within the configuration register at the receiver is set to a second value.

33. The method of claim 31, further comprising:

receiving a third datagram from the transmitter for setting another single bit within the configuration register at the receiver;

detecting that a page segmented access operation is enabled when the other single bit within the configuration register at the receiver is set to a first value, wherein an address of the RFFE register is a combination of an address value located at a page address register at the receiver and the address value provided by the second datagram when the page segmented access operation is enabled; and

detecting that the page segmented access operation is disabled when the other single bit within the configuration register at the receiver is set to a second value, wherein the address of the RFFE register is the address value provided by the second datagram when the page segmented access operation is disabled.

34. A receiver for receiving data from a transmitter, comprising:

a bus interface; and

a processing circuit configured to;

receive a first datagram from the transmitter for setting a single bit within a configuration register at the receiver,

detect that a masked-write operation is enabled when the single bit within the configuration register is set to a first value,

receive a second datagram from the transmitter, the second datagram providing an address value,

read a payload field in the second datagram, the payload field including a number of mask-and-data pairs when the masked-write operation is enabled, wherein each mask-and-data pair includes a mask field identifying at least one bit to be changed in a radio frequency front end (RFFE) register of the receiver and a data field providing a value of the at least one bit to be changed in the RFFE register, and

change the at least one bit in the RFFE register identified in the mask field according to the value provided in the data field for each mask-and-data pair.

35. The receiver of claim 34, the processing circuit further configured to:

detect that the masked-write operation is disabled when the single bit within the configuration register at the receiver is set to a second value.

36. The receiver of claim 34, the processing circuit further configured to:

receive a third datagram from the transmitter for setting another single bit within the configuration register at the receiver;

detect that a page segmented access operation is enabled when the other single bit within the configuration register at the receiver is set to a first value, wherein an address of the RFFE register is a combination of an address value located at a page address register at the receiver and the address value provided by the second datagram when the page segmented access operation is enabled; and

detect that the page segmented access operation is disabled when the other single bit within the configuration register at the receiver is set to a second value, wherein the address of the RFFE register is the address value provided by the second datagram when the page segmented access operation is disabled.