TOP PINNED SOT-MRAM ARCHITECTURE WITH IN-STACK SELECTOR

• US 20170117027A1
• Filed: 10/21/2015
• Published: 04/27/2017
• Est. Priority Date: 10/21/2015
• Status: Abandoned Application

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: HGST Netherlands B.V. (Western Digital Corporation)
• Inventors: BRAGANCA, Patrick M., WAN, Lei
• Application Number:
  US14/919,247
• Publication Number:
  US 20170117027A1
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/18 using Hall-effect devices
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM cell and chip architecture. The SOT-MRAM chip architecture includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells. Each memory cell of the plurality of memory cells includes a MTJ and a selector element. These SOT-MRAM cells eliminate the need to pass large currents through the barrier layer of the MTJ and the selector element eliminates the large transistors usually required for selecting a single memory cell without disturbing neighboring memory cells.

Claims

1. A memory cell, comprising:

a magnetic tunnel junction; and

a selector element disposed on the magnetic tunnel junction.

2. The memory cell of claim 1, wherein the magnetic tunnel junction comprises:

a ferromagnetic free layer;

a barrier layer disposed on and in contact with the ferromagnetic free layer;

a ferromagnetic reference layer disposed on and in contact with the barrier layer; and

a capping layer disposed on and in contact with the ferromagnetic reference layer, wherein the selector is disposed on and in contact with the capping layer.

3. The memory cell of claim 2, wherein the ferromagnetic free layer has a magnetic polarization in a film plane or perpendicular to the film plane.

4. The memory cell of claim 2, wherein the ferromagnetic reference layer has a magnetic polarization in a film plane or perpendicular to the film plane.

5. The memory cell of claim 1, wherein the selector element is a Schottky diode having a metal layer and a semiconductor layer.

6. The memory cell of claim 1, wherein the selector element is a semiconductor diode having a p-n junction.

7. A memory cell array, comprising:

a plurality of first leads;

a plurality of second leads; and

a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads, wherein each memory cell of the plurality of memory cells comprises;

a magnetic tunnel junction; and

a selector element disposed on the magnetic tunnel junction.

8. The memory cell array of claim 7, wherein each memory cell of the plurality of memory cells is disposed at a location that a first lead of the plurality of first leads and a second lead of the plurality of second leads cross over.

9. The memory cell array of claim 7, wherein the magnetic tunnel junction of each memory cell of the plurality of memory cells comprises:

a ferromagnetic free layer;

a barrier layer disposed on and in contact with the ferromagnetic free layer;

a ferromagnetic reference layer disposed on and in contact with the barrier layer; and

a capping layer disposed on and in contact with the ferromagnetic reference layer, wherein the selector is disposed on and in contact with the capping layer.

10. The memory cell array of claim 9, wherein the ferromagnetic free layer is disposed on and in contact with a second lead of the plurality of second leads, and a first lead of the plurality of first leads is disposed on and in contact with the selector.

11. The memory cell array of claim 7, wherein each first lead of the plurality of first leads has a lower electrical resistivity than each second lead of the plurality of second leads.

12. The memory cell array of claim 11, wherein each first lead of the plurality of first leads comprises copper or aluminum and each second lead of the plurality of second leads comprises a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW, and wherein a writing process is performed by a half-select mechanism that includes a combination of flowing a current along a second lead of the plurality of second leads and applying a voltage to a first lead of the plurality of first leads.

13. The memory cell array of claim 7, wherein the selector element comprises a diode.

14. The memory cell array of claim 13, wherein the diode is a semiconductor diode having a p-n junction.

15. The memory cell array of claim 7, wherein the selector element is a Schottky diode having a metal layer and a semiconductor layer.

16. A spin-orbit torque magnetoresistive random access memory, comprising:

a memory cell array, comprising;

a plurality of first leads;

a plurality of second leads; and

a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads, wherein each memory cell of the plurality of cells comprises;

a magnetic tunnel junction; and

a selector element disposed on the magnetic tunnel junction.

17. The spin-orbit torque magnetoresistive random access memory of claim 16, wherein the magnetic tunnel junction of each memory cell of the plurality of memory cells comprises:

a ferromagnetic free layer;

a barrier layer disposed on and in contact with the ferromagnetic free layer;

a ferromagnetic reference layer disposed on and in contact with the barrier layer; and

a capping layer disposed on and in contact with the ferromagnetic reference layer, wherein the selector is disposed on and in contact with the capping layer.

18. The spin-orbit torque magnetoresistive random access memory of claim 17, wherein the ferromagnetic free layer is disposed on and in contact with a second lead of the plurality of second leads, and a first lead of the plurality of first leads is disposed on and in contact with the selector.

19. The spin-orbit torque magnetoresistive random access memory of claim 16, wherein each first lead of the plurality of first leads has a lower electrical resistivity than each second lead of the plurality of second leads.

20. The spin-orbit torque magnetoresistive random access memory of claim 19, wherein each first lead of the plurality of first leads comprises copper or aluminum and each second lead of the plurality of second leads comprises a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW, and wherein a writing process is performed by a half-select mechanism that includes a combination of flowing a current along a second lead of the plurality of second leads and applying a voltage to a first lead of the plurality of first leads.