SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20170117192A1
• Filed: 07/21/2016
• Published: 04/27/2017
• Est. Priority Date: 10/26/2015
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Gi-Gwan, KANG, Sang-Koo, KIM, Ju-Youn, RYU, Koung-Min, LEE, Jae-Hoon, HA, Tae-Won, Min, Sun-Ki, KIM, Sung-Sao
• Application Number:
  US15/215,951
• Publication Number:
  US 20170117192A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A semiconductor device may include a first gate electrode being formed on a substrate and having a first ratio of a width of an upper surface to a width of a lower surface, a second gate electrode being formed on the substrate and having a second ratio of the width of the upper surface to the width of the lower surface, wherein the second ratio is less than the first ratio, a first gate spacer being formed on a sidewall of the first gate electrode, a second gate spacer being formed on a sidewall of the second gate electrode and an interlayer insulating film covering the first gate spacer and the second gate spacer.

Claims

1. A semiconductor device, comprising:

a first gate electrode on a substrate, the first gate electrode having a first ratio of a width of an upper surface thereof to a width of a lower surface thereof;

a second gate electrode on the substrate, the second gate electrode having a second ratio of a width of an upper surface thereof to a width of a lower surface thereof such that the second ratio is less than the first ratio;

a first gate spacer on a sidewall of the first gate electrode;

a second gate spacer on a sidewall of the second gate electrode; and

an interlayer insulating film at least partially covering the first gate spacer and the second gate spacer.

2. The semiconductor device of claim 1, wherein the first ratio is greater than or equal to 1, and the second ratio is less than or equal to 1.

3. The semiconductor device of claim 1, wherein the first ratio and the second ratio are greater than or equal to 1.

4. The semiconductor device of claim 1, wherein the first ratio and the second ratio are less than or equal to 1.

5. The semiconductor device of claim 1, wherein the first gate electrode is an N-type gate electrode, and the second gate electrode is a P-type gate electrode.

6. The semiconductor device of claim 5, wherein

the first gate electrode includes an N-type work function metal, and

the second gate electrode includes an N-type work function metal and a P-type work function metal.

7. The semiconductor device of claim 1, wherein a width of the first gate electrode gradually decreases from the upper surface of the substrate to the upper surface of the first gate electrode.

8. The semiconductor device of claim 7, wherein a width of the second gate electrode gradually increases from the upper surface of the substrate to the upper surface of the second gate electrode.

9. The semiconductor device of claim 1, wherein the first gate spacer comprises:

a first nitride spacer on the sidewall of the first gate electrode;

a first oxide spacer on the first nitride spacer; and

a first stress spacer on the first oxide spacer.

10. The semiconductor device of claim 9, wherein the second gate spacer comprises:

a second nitride spacer on the sidewall of the second gate electrode;

a second oxide spacer on the second nitride spacer; and

a second stress spacer on the second oxide spacer.

11. The semiconductor device of claim 10, wherein a thickness of the first oxide spacer is different than a thickness of the second oxide spacer.

12. The semiconductor device of claim 10, wherein the first stress spacer and the second stress spacer are connected via stepped connecting portions.

13. A semiconductor device, comprising:

a first gate electrode on a substrate such that a width of the first gate electrode increases with increasing distance from the substrate;

a second gate electrode on the substrate such that a width of the second gate electrode decreases with increasing distance from the substrate;

a first gate spacer on a sidewall of the first gate electrode, the first gate spacer configured to exert a first tensile stress on the first gate electrode;

a second gate spacer on a sidewall of the second gate electrode, the second gate spacer configured to exert a second tensile stress on the second gate electrode such that the first tensile stress exerted on the first gate electrode is greater than the second tensile stress exerted on the second gate electrode; and

an interlayer insulating film at least partially covering the first gate spacer and the second gate spacer.

14. The semiconductor device of claim 13, wherein the interlayer insulating film is configured to exert a compressive stress on the second gate electrode.

15. The semiconductor device of claim 13, wherein the first gate spacer comprises:

a first nitride spacer on the sidewall of the first gate electrode;

a first oxide spacer on the first nitride spacer; and

a first stress spacer on the first oxide spacer, the first stress spacer configured to exert the first tensile stress on the first gate electrode.

16. A semiconductor device, comprising:

a first gate spacer on sidewalls of a first gate electrode such that the first gate spacer is configured to exert a first tensile stress on the first gate electrode;

a second gate spacer on sidewalls of a second gate electrode such that the first gate spacer is configured to exert a second tensile stress on the second gate electrode; and

an interlayer insulating film at least partially covering the first gate spacer and the second gate spacer such that the interlayer insulating film is configured to exert a first compressive stress on the first gate electrode and a second compressive stress on the second gate electrode.

17. The semiconductor device of claim 16, wherein the first gate electrode and the second gate electrode each have a lower surface on a substrate such that a first width associated with the first gate electrode increases from the lower surface to an upper surface thereof, and a second width associated with the second gate electrode decreases from the lower surface to an upper surface thereof.

18. The semiconductor device of claim 17, wherein the first tensile stress is greater than the second tensile stress such that the first width increases and the second width decreases as a distance increases from the substrate to the upper surfaces of the first gate electrode and the second gate electrode, respectively.

19. The semiconductor device of claim 18, wherein the first tensile stress is greater than the first compressive stress.

20. The semiconductor device of claim 18, wherein the first gate electrode is doped with an N-type material and the second gate electrode is doped with a P-type material such that the first gate electrode and the second gate electrode experience a net tensile stress and a net compressive stress, respectively.