SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME

• US 20170117198A1
• Filed: 10/20/2016
• Published: 04/27/2017
• Est. Priority Date: 10/21/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Jong-Hyun Choi, Joung-Yeal Kim, Mi-Young Woo
• Inventors: KIM, Joung-Yeal, KWON, Dae-Hyun, WOO, Mi-Young, CHOI, Jong-Hyun, YOON, Joon-Sun
• Granted Patent: US 9,966,317 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 28/20 Resistors

Abstract

A semiconductor device may include a first terminal electrically connected to a first semiconductor chip, a second terminal electrically connected to a second semiconductor chip, which is different from the first semiconductor chip, a first signal line electrically connecting the first terminal and the second terminal and including a first node, a third terminal connected to a tester monitoring a signal transmitted between the first semiconductor chip and the second semiconductor chip, a fourth terminal applied a reference voltage, a second signal line electrically connecting the third terminal and the fourth terminal and including a second node, a first resistor connected between the first node and the second node and a second resistor directly connected to the second node different from the first resistor.

Claims

1. A semiconductor device, comprising:

a first terminal electrically connected to a first semiconductor chip;

a second terminal electrically connected to a second semiconductor chip;

a first signal line configured to electrically connect the first terminal and the second terminal;

a third terminal configured to electrically connect to a tester, the tester configured to monitor a signal transmitted between the first semiconductor chip and the second semiconductor chip;

a second signal line configured to electrically connect the third terminal and a fourth terminal, the fourth terminal configured to receive a reference voltage;

a first resistor electrically connected between a first node associated with the first signal line and a second node associated with the second signal line; and

a second resistor electrically connected between the second node and the fourth terminal.

2. The semiconductor device of claim 1, further comprising:

an interposer configured to electrically connect the tester to the semiconductor device.

3. The semiconductor device of claim 1, wherein the reference voltage is a power supply voltage.

4. The semiconductor device of claim 1, wherein a sum of a resistance of resistor components of the tester and a resistance of the second resistor equals a resistance of the first resistor.

5. The semiconductor device of claim 1, wherein the second resistor and the first resistor are connected in parallel to the second node.

6. A semiconductor package, comprising:

a circuit board including a reference voltage terminal configured to receive a reference voltage;

an interposer electrically connected to the circuit board, the interposer including a tester terminal; and

a first semiconductor chip on the interposer, the first semiconductor chip configured to electrically connect to the circuit board and the interposer, the interposer including,

a first wire configured to electrically connect the circuit board and the first semiconductor chip,

a second wire configured to electrically connect to the first wire includes a first resistor, and

a third wire configured to electrically connect the tester terminal and the reference voltage terminal, the third wire including a second resistor.

7. The semiconductor package of claim 6, wherein the reference voltage is a power supply voltage.

8. The semiconductor package of claim 6, wherein

the second wire includes a first region and a second region each having a different electrical conductivity, the second region having the first resistor associated therewith, and

the third wire includes a third region and a fourth region each having a different electrical conductivity, the fourth region having the second resistor associated therewith.

9. The semiconductor package of claim 8, wherein the electrical conductivity of the second region differs from the electrical conductivity of the fourth region.

10. The semiconductor package of claim 8, wherein

the electrical conductivity of the first region is higher than the electrical conductivity of the second region, and

the electrical conductivity of the third region is higher than the electrical conductivity of the fourth region.

11. The semiconductor package of claim 6, wherein the second wire is electrically connected to the third wire.

12. The semiconductor package of claim 6, further comprising:

a second semiconductor chip electrically connected to the circuit board and electrically isolated from the interposer, the second semiconductor chip electrically connected to the first wire.

13. The semiconductor package of claim 12., wherein the tester terminal is configured to connect to a tester, the tester being configured to monitor a signal transmitted between the first semiconductor chip and the second semiconductor chip.

14. The semiconductor package of claim 6, wherein

the first wire electrically connects a first terminal associated with the first semiconductor chip and a second terminal associated with the circuit board,

the first semiconductor chip is electrically connected to the interposer via the first terminal, and

the circuit board is electrically connected to the interposer via the second terminal.

15. The semiconductor package of claim 13, wherein a sum of a resistance of resistor components of the tester and a resistance of the second resistor equals a resistance of the first resistor.

16. A semiconductor device comprising:

an interposer configured to electrically connect a testing device to a first signal path between a first semiconductor chip and a second semiconductor chip, the testing device configured to monitor a signal transmitted via the first signal path between the first semiconductor chip and the second semiconductor chip, the interposer including,

a first resistor configured to electrically connect a first node and a second node, the first node being anode on the first signal path between the first semiconductor chip and the second semiconductor chip and the second node being a node on a second signal path between the first node and the testing device, and

a second resistor configured to electrical connect a reference terminal and the second node, the reference terminal configured to receive a reference voltage.

17. The semiconductor device of claim 16, wherein the first signal path includes a first line configured to electrically connect the first semiconductor chip and the second semiconductor chip and the second signal path includes a second line and a third line, the second line configured to electrically connect the first node and the second node, and the third line configured to electrically connect the testing device to the second node.

18. The semiconductor device of claim 17, wherein the first line is configured to electrically connect the first semiconductor chip and a circuit board having the second semiconductor chip thereon such that the second semiconductor chip is electrically connected to the interposer via the circuit board.

19. The semiconductor device of claim 16, wherein the first resistor has a resistance equal to a sum of a resistance of the testing device and a resistance of the second resistor.

20. The semiconductor device of claim 16, wherein

the first resistor is configured to reduce distortion in the signal transmitted between the first semiconductor chip and the second semiconductor chip, and

the second resistor is configured to compensate for an effect of termination of the testing device.