VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

• US 20170117222A1
• Filed: 07/12/2016
• Published: 04/27/2017
• Est. Priority Date: 10/22/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hyuk Kim, Jae-Ho Min, Seung-Pil Chung
• Inventors: KIM, Hyuk, CHUNG, Seung-Pil, MIN, Jae-Ho, PARK, Jong-Kyoung
• Granted Patent: US 9,865,540 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A vertical memory device includes a plurality of gate lines, at least one etch-stop layer, channels, and contacts. The gate lines are stacked and spaced apart from each other along a first direction with respect to a surface of substrate. Each of the gate lines includes step portion protruding in a second direction. The at least one etch-stop layer covers the step portion of at least one of the gate lines and includes conductive material. The channels extend through the gate lines in the first direction. The contacts extend through the at least one etch-stop layer and are on the step portions of the gate lines.

Claims

1. A vertical memory device, comprising:

a substrate;

a plurality of gate lines stacked and spaced apart from each other along a first direction that extends vertically with respect to a surface of the substrate, each of the gate lines including a gate step portion protruding in a second direction that is different from the first direction;

at least one etch-stop layer covering the gate step portion of at least one of the gate lines and including a conductive material;

channels extending through the gate lines in the first direction; and

contacts extending through the at least one etch-stop layer and on the gate step portions.

2. The vertical memory device as claimed in claim 1, further comprising:

insulating interlayer patterns spaced apart from each other by the gate lines along the first direction, each of the insulating interlayer patterns including an insulating step portion protruding in the second direction.

3. The vertical memory device as claimed in claim 2, wherein the at least one etch-stop layer includes:

a first etch-stop layer arranged along the insulating step portions, the first etch-stop layer including an oxide; and

a second etch-stop layer on the first etch-stop layer and including a conductive material.

4. The vertical memory device as claimed in claim 3, wherein the second etch-stop layer includes a same metal as in the gate lines.

5. The vertical memory device as claimed in claim 3, wherein the first etch-stop layer includes a same oxide as in the insulating interlayer patterns.

6. The vertical memory device as claimed in claim 3, wherein the second etch-stop layer is divided per each insulating step portion of the insulating interlayer patterns.

7. The vertical memory device as claimed in claim 1, wherein the contacts are physically separated from the at least one etch-stop layer.

8. The vertical memory device as claimed in claim 7, further comprising:

a plurality of contact spacers surrounding sidewalls of the contacts.

9. The vertical memory device as claimed in claim 1, wherein the at least one etch-stop layer covers gate step portions of at least some of the gate lines.

10. The vertical memory device as claimed in claim 9, wherein the gate lines include a ground selection line (GSL), word lines, and a string selection line (SSL) sequentially stacked from the surface of the substrate.

11. The vertical memory device as claimed in claim 10, wherein the at least one etch-stop layer only covers gate step portions of the gate selection line and the word lines.

12. The vertical memory device as claimed in claim 10, wherein the at least one etch-stop layer only covers gate step portions of predetermined ones of the word lines.

13. The vertical memory device as claimed in claim 1, wherein the substrate includes:

a cell region on which the channels are disposed;

an extension region on which the step portions of the gate lines are disposed; and

a peripheral circuit region, wherein the at least one etch-stop layer is only on the cell region and the extension region.

14. A vertical memory device, comprising:

a substrate;

a gate line stack structure on the substrate and including;

gate lines stacked and spaced apart from each other in a first direction that extends vertically with respect to a surface of the substrate;

insulating interlayer patterns stacked and spaced apart from each other by the gate lines in the first direction; and

channels extending through the insulating interlayer patterns and the gate lines in the first direction;

a first etch-stop layer on the gate line stack structure and including an insulation material;

a second etch-stop layer on the first etch-stop layer and including a conductive material; and

contacts extending through the second etch-stop layer and the first etch-stop layer, the contacts being electrically connected to the gate lines.

15. The vertical memory device as claimed in claim 14, wherein:

the insulating interlayer patterns and the gate lines are alternately stacked along the first direction in a stepped shape,

the insulating interlayer patterns and the gate lines include step portions protruding in a second direction that is different from the first direction, and

the step portions of the gate lines are covered by the step portions of the insulating interlayer patterns.

16. A memory device, comprising:

a substrate;

a plurality of gate lines stacked on the substrate;

a plurality of insulating layers between the gate lines respectively, the gate lines and insulating layers arranged in steps;

a first etch-stop layer on the steps and including a first material;

a second etch-stop layer on the first etch-stop layer and including a second material different from the first material;

channels extending through the gate lines; and

contacts extending through the first and second etch-stop layers to contact respective ones of the gate lines through corresponding ones of the insulating layers.

17. The memory device as claimed in claim 16, wherein:

the first material is an insulation material, and

the second material is a conductive material.

18. The memory device as claimed in claim 17, wherein:

the first etch-stop layer and the insulating layers include an oxide, and

the second-etch stop layer and the gate lines include a metal.

19. The memory device as claimed in claim 16, wherein the gate lines include a ground selection line, word lines, and a string selection line sequentially stacked from the substrate.

20. The memory device as claimed in claim 19, wherein the first and second etch-stop layers cover only step portions of predetermined ones of the ground selection line and the word lines.