Interconnection Structure and Method of Forming Same

• US 20170117245A1
• Filed: 11/14/2016
• Published: 04/27/2017
• Est. Priority Date: 09/18/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yu-Wei, Wu, Sheng-Yu, Tseng, Yu-Jen, Kuo, Tin-Hao, Chen, Chen-Shien
• Granted Patent: US 10,319,691 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/02125 Reinforcing structures
• CPC Class Codes: H01L 2224/02141 Multilayer auxiliary member
• CPC Class Codes: H01L 2224/02145 Shape of the auxiliary member
• CPC Class Codes: H01L 2224/0215 Material of the auxiliary member
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05114 Thallium [Tl] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/10125 Reinforcing structures
• CPC Class Codes: H01L 2224/11013 for holding or confining the bump connector, e.g. solder flow barrier
• CPC Class Codes: H01L 2224/11019 for protecting parts during the process
• CPC Class Codes: H01L 2224/1112 Applying permanent coating
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11472 Profile of the lift-off mask
• CPC Class Codes: H01L 2224/13005 Structure
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13013 : being rectangular or square
• CPC Class Codes: H01L 2224/13014 : being circular or elliptic
• CPC Class Codes: H01L 2224/13015 : comprising protrusions or indentations
• CPC Class Codes: H01L 2224/13017 : being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13023 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13026 : relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1308 : being stacked
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 : Three-layer arrangements
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13551 : being non uniform
• CPC Class Codes: H01L 2224/13564 : Only on the bonding interface of the bump connector
• CPC Class Codes: H01L 2224/13565 : Only outside the bonding interface of the bump connector
• CPC Class Codes: H01L 2224/1357 : Single coating layer
• CPC Class Codes: H01L 2224/13582 : Two-layer coating
• CPC Class Codes: H01L 2224/136 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13686 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/1369 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/14051 : Bump connectors having different shapes
• CPC Class Codes: H01L 2224/16148 : the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/16503 : comprising an intermetallic compound
• CPC Class Codes: H01L 2224/81007 : involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
• CPC Class Codes: H01L 2224/81143 : Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81424 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/81439 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/81444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/8181 : involving forming an intermetallic compound at the bonding interface
• CPC Class Codes: H01L 2224/81895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/8192 : Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/81948 : Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/053 : Oxides composed of metals from groups of the periodic table
• CPC Class Codes: H01L 2924/05432 : Al2O3
• CPC Class Codes: H01L 2924/07025 : Polyimide
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/301 : Electrical effects
• CPC Class Codes: H01L 2924/35 : Mechanical effects
• CPC Class Codes: Y10T 29/49144 : by metal fusion

Abstract

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Claims

1. A method of forming semiconductor device, the method comprising:

mounting a substrate trace on a first substrate, the substrate trace having a first tapering profile; and

coupling a metal ladder bump on a second substrate and the substrate trace together through direct metal-to-metal bonding, the metal ladder bump having a second tapering profile, the first substrate and the second substrate being bonded without use of solder.

2. The method of claim 1, wherein mounting the substrate trace comprises using an electrolytic plating process.

3. The method of claim 1, wherein coupling the metal ladder bump and the substrate trace comprises using thermo-compression bonding.

4. The method of claim 1, further comprising subjecting the metal ladder bump and the substrate trace to an annealing processing using a temperature of about 100°

C. to about 400°

C. for about 1 hour to about 2 hours.

5. The method of claim 1, further comprising:

forming a contact pad on the first substrate;

forming one or more insulating layers over the contact pad, the one or more insulating layers having an opening exposing the contact pad; and

forming an under bump metallization in the opening, the under bump metallization extending over an outermost surface of the one or more insulating layers, wherein the metal ladder bump is formed on the under bump metallization.

6. The method of claim 5, wherein the metal ladder bump extends into the opening in the one or more insulating layers.

7. The method of claim 6, wherein the metal ladder bump extends closer to the contact pad than an outermost surface of a first insulating layer of the one or more insulating layers, the first insulating layer directly contacting the contact pad.

8. A method of forming a semiconductor device, the method comprising:

bonding a first conductive element to a second conductive element, the first conductive element being on a first substrate and having a first tapered profile, the second conductive element being on a second substrate and having a second tapered profile, the first conductive element and the second conductive element being bonded without use of solder.

9. The method of claim 8, wherein a ratio of a first width of a first distal end of the first conductive element from the first substrate to a second width of a mounted end of the first conductive element is between about 0.75 to about 0.97.

10. The method of claim 9, wherein a ratio of a third width of a second distal end of the second conductive element from the second substrate to a fourth width of a mounted end of the second conductive element is between about 0.75 to about 0.97.

11. The method of claim 8, wherein the bonding comprises performing thermo-compression bonding of the first conductive element to the second conductive element.

12. The method of claim 11, wherein the bonding comprises annealing to increase a bond strength between the first conductive element and the second conductive element.

13. The method of claim 12, wherein the annealing is performed at a temperature between 100°

C. and 400°

C.

14. The method of claim 13, wherein the annealing is performed for a period of 1 hour to 2 hours.

15. A method of forming a semiconductor device, the method comprising:

aligning a first conductive element of a first substrate to a second conductive element of a second substrate, a first width of the first conductive element decreases as the first conductive element extends away from the first substrate, a second width of the second conductive element decreases as the second conductive element extends away from the second substrate; and

bonding the first conductive element to the second conductive element without using solder.

16. The method of claim 15, further comprising:

forming a contact element in a low-k dielectric layer;

forming a first passivation layer over the low-k dielectric layer, the first passivation layer having a first opening exposing the contact element;

forming a second passivation layer over the first passivation layer, the second passivation layer having a second opening exposing the contact element; and

forming the first conductive element extending through the first opening and the second opening.

17. The method of claim 16, wherein the second passivation layer completely separates the first passivation layer from the first conductive element.

18. The method of claim 15, wherein the first width at a first distal end from the first substrate is different than the second width at a second distal end from the second substrate.

19. The method of claim 15, wherein a height of the first conductive element is greater than a height of the second conductive element.

20. The method of claim 15, wherein the first substrate comprises a first chip and the second substrate comprises a second chip.