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SEMICONDUCTOR MEMORY DEVICE, STRUCTURE AND METHODS

  • US 20170117291A1
  • Filed: 10/24/2016
  • Published: 04/27/2017
  • Est. Priority Date: 10/24/2015
  • Status: Active Grant
First Claim
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1. A multilevel semiconductor device, comprising:

  • a first level comprising a first array of first memory cells;

    a second level comprising a second array of second memory cells, said first level is overlaid by said second level,wherein at least one of said first memory cells comprises a vertically oriented first transistor, andwherein at least one of said second memory cells comprises a vertically oriented second transistor, andwherein said first transistor comprises a first single crystal channel, andwherein said second transistor comprises a second single crystal channel, andwherein said first transistor is self aligned to said second transistor.

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