SEMICONDUCTOR MEMORY DEVICE, STRUCTURE AND METHODS

• US 20170117291A1
• Filed: 10/24/2016
• Published: 04/27/2017
• Est. Priority Date: 10/24/2015
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Han, Jin-Woo
• Granted Patent: US 10,014,318 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 53/20 characterised by the three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A multilevel semiconductor device, including: a first level including a first array of first memory cells; a second level including a second array of second memory cells, the first level is overlaid by the second level, where at least one of the first memory cells includes a vertically oriented first transistor, and where at least one of the second memory cells includes a vertically oriented second transistor, and where the first transistor includes a first single crystal channel, and where the second transistor includes a second single crystal channel, and where the first transistor is self-aligned to the second transistor.

Claims

1. A multilevel semiconductor device, comprising:

a first level comprising a first array of first memory cells;

a second level comprising a second array of second memory cells, said first level is overlaid by said second level,

wherein at least one of said first memory cells comprises a vertically oriented first transistor, and

wherein at least one of said second memory cells comprises a vertically oriented second transistor, and

wherein said first transistor comprises a first single crystal channel, and

wherein said second transistor comprises a second single crystal channel, and

wherein said first transistor is self aligned to said second transistor.

2. The multilevel semiconductor device of claim 1,

wherein said first single crystal channel is aligned to said second single crystal channel at an atomic level.

3. The multilevel semiconductor device of claim 1,

wherein said first transistor comprises a first transistor drain, and

wherein said second transistor comprises a second transistor source, and

wherein said first transistor drain is shared with said second transistor source.

4. The multilevel semiconductor device of claim 1,

wherein said first transistor comprises a first transistor drain, and

wherein said first array comprises a third memory cell comprising a third transistor and a third transistor drain, and

wherein said third transistor drain is directly connected to said first transistor drain.

5. The multilevel semiconductor device of claim 1,

wherein said first transistor comprises a first drain, and

wherein said first level comprise at least one memory bit-line, and

wherein said bit-line is partially shared with said first transistor drain.

6. The multilevel semiconductor device of claim 1,

wherein said first transistor comprises a first transistor drain, and

wherein said first transistor drain is at least partially silicided.

7. The multilevel semiconductor device of claim 1,

wherein said first transistor comprises a Schottky Barrier drain.

8. The multilevel semiconductor device of claim 1,

wherein said first transistor comprises a Dopant Segregated Schottky Barrier drain.

9. A multilevel semiconductor device, comprising:

a first level comprising a first array of first memory cells;

a second level comprising a second array of second memory cells, said first level is overlaid by said second level,

wherein at least one of said first memory cells comprises a vertically oriented first transistor, and

wherein at least one of said second memory cells comprises a vertically oriented second transistor, and

wherein said first transistor comprises a first single crystal channel, and

wherein said second transistor comprises a second single crystal channel, and

wherein said first level comprises at least one memory bit-line, and

wherein said bit-line comprises a horizontal transistor, said horizontal transistor controls a current drive within at least said bit-line.

10. The device according to claim 9,

wherein said horizontal transistor is a junction-less transistor.

11. The device according to claim 9

wherein said horizontal transistor comprises a Schottky Barrier drain or source.

12. The device according to claim 9,

wherein said horizontal transistor comprises a Dopant Segregated Schottky Barrier drain or source.

13. A multilevel semiconductor device, comprising:

a first level comprising a first array of first memory cells;

a second level comprising a second array of second memory cells, said first level is overlaid by said second level,

wherein at least one of said first memory cells comprises a vertically oriented first transistor, and

wherein at least one of said second memory cells comprises a vertically oriented second transistor, and

wherein said first transistor comprises a first single crystal channel, and

wherein said second transistor comprises a second single crystal channel, and

wherein said second level is overlaid with a third level, and

wherein said third level comprises memory control circuits, said memory control circuits control at least one a read or write operation to said first memory cell.

14. The multilevel semiconductor device of claim 13:

wherein said first transistor is an asymmetric transistor.

15. The multilevel semiconductor device of claim 13:

wherein said first level comprises at least one memory bit-line, and

wherein said bit-line is shared between said first level and said second level.

16. The multilevel semiconductor device of claim 13:

wherein said first level comprises at least one memory bit-line, and

wherein said bit-line is shared between said first level and said second level, and

wherein said bit-line has regions of isolation disposed all-around said bit line.

17. The multilevel semiconductor device of claim 13:

wherein said first level comprises at least one memory bit-line, and

wherein said bit-line is shared between said first level and said second level, and

wherein said bit-line is connected to an inline staircase structure.

18. The multilevel semiconductor device of claim 13:

wherein said first level comprises at least one memory bit-line, and

wherein said bit-line is shared between said first level and said second level, and

wherein said bit-line is connected to a staircase structure disposed perpendicularly with respect to said bit-line.

19. The multilevel semiconductor device of claim 13,

wherein said first channel comprises at least 5% Ge atoms.

20. The multilevel semiconductor device of claim 13:

wherein said first transistor comprises a charge trap gate stack.