Rear-face illuminated solid state image sensors

• US 20170117318A1
• Filed: 10/31/2016
• Published: 04/27/2017
• Est. Priority Date: 11/05/2010
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: DigitalOptics Corporation East (Adeia Inc.), Tessera North America Incorporated (Adeia Inc.)
• Inventors: Humpston, Giles, Kriman, Moshe
• Granted Patent: US 10,249,673 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14806 Structural or functional details thereof

Abstract

A microelectronic unit includes a semiconductor element having a front surface to which a packaging layer is attached, and a rear surface remote from the front surface. The element includes a light detector including a plurality of light detector element arranged in an array disposed adjacent to the front surface and arranged to receive light through the rear surface. The semiconductor element also includes an electrically conductive contact at the front surface connected to the light detector. The conductive contact includes a thin region and a thicker region which is thicker than the thin region. A conductive interconnect extends through the packaging layer to the thin region of the conductive contact, and a portion of the conductive interconnect is exposed at a surface of the microelectronic unit.

Claims

1. A microelectronic unit comprising:

a semiconductor element having a front surface, an opposed rear surface, and a bonding contact disposed at least partially adjacent the front surface;

a packaging layer overlying the semiconductor element;

an image sensing region including light detector elements disposed adjacent a rear surface of the semiconductor element;

a terminal overlying an outermost surface of the packaging layer; and

a conductive via extending through the packaging layer and at least a portion of the bonding contact so as to form an interior wall surface within the bonding contact, the via electrically connecting the terminal and the bonding contact,

wherein the image sensing region is electrically isolated from the conductive via.

2. The microelectronic unit of claim 1, wherein the image sensing region further includes an image sensor disposed within the semiconductor element.

3. The microelectronic unit of claim 2, wherein the image sensor is a charge-coupled device array.

4. The microelectronic unit of claim 1, wherein the conductive via further comprises a conductive layer extending therethrough and contacting the interior wall surface of the bonding contact.

5. The microelectronic unit of claim 4, wherein the conductive layer extends onto the outermost surface of the packaging layer and forms the terminal.

6. The microelectronic unit of claim 1, wherein a continuous layer of conductive material extends between the terminal and the bonding contact, an end of the continuous layer of conductive material forming the terminal.

7. The microelectronic unit of claim 1, further comprising a packaging assembly joined to the semiconductor element, at least a portion of the packaging assembly and the semiconductor element being spaced apart from one another so as to form a recess within the microelectronic unit, the light detector elements disposed within the recess.

8. The microelectronic unit of claim 7, wherein the packaging assembly further includes a second packaging layer.

9. The microelectronic unit of claim 8, wherein the conductive via extends through the second packaging layer.

10. The microelectronic unit of claim 8, wherein the second packaging layer has a thickness of no less than 30 microns.

11. The microelectronic unit of claim 1, further comprising an adhesive layer joining the packaging layer and semiconductor layer together.

12. The microelectronic unit of claim 11, wherein the conductive via extends through the adhesive layer.

13. The microelectronic unit of claim 1, further comprising an isolation region configured to isolate the image sensing region from the conductive via, the isolation region at least partially defined by a rear surface of the bonding contact and a rear surface of the semiconductor element.

14. The microelectronic unit of claim 13, wherein the isolation region further comprises a trench disposed between the image sensing region and the bonding contact.

15. The microelectronic unit of claim 1, wherein the conductive via extends through a front surface of the bonding contact.

16. The microelectronic unit of claim 14, wherein the conductive via further extends through the rear surface of the bonding contact.