Bulk Nanosheet with Dielectric Isolation

• US 20170117359A1
• Filed: 10/21/2015
• Published: 04/27/2017
• Est. Priority Date: 10/21/2015
• Status: Active Grant

• Current Assignee: Tessera (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Wang, Junli
• Granted Patent: US 9,741,792 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76213 introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Claims

1. A method of forming a nanosheet device structure with dielectric isolation, the method comprising the steps of:

forming a plurality of nanosheets as a stack on the bulk semiconductor wafer;

patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks;

forming spacers covering sidewalls of the nanowire stacks; and

oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in a top portion of the bulk semiconductor wafer.

2. The method of claim 1, further comprising the step of:

implanting at least one dopant into the top portion of the bulk semiconductor wafer prior to performing the step of forming the nanosheets on the bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer;

3. The method of claim 2, wherein the at least one dopant is selected from the group consisting of:

fluorine, phosphorous, and combinations thereof.

4. The method of claim 2, wherein the at least one dopant is implanted into the top portion of the bulk semiconductor wafer at a dose of from about from about 5×

10¹⁵ to about 5×

10¹⁶, and ranges therebetween.

5. The method of claim 1, wherein the bulk semiconductor wafer has a thickness of from about 0.1 millimeters to about 0.75 millimeters, and ranges therebetween.

6. The method of claim 1, wherein the top portion of the bulk semiconductor wafer comprises a first from about 100 angstroms to about 500 angstroms, and ranges therebetween, of the bulk semiconductor wafer.

7. The method of claim 1, wherein the plurality of nanosheets comprises alternating layers of a sacrificial material and a channel material as the stack on the bulk semiconductor wafer.

8. The method of claim 7, wherein the sacrificial material comprises silicon germanium (SiGe) and the channel material comprises silicon (Si).

9. The method of claim 1, wherein a first nanosheet in the stack present on the bulk semiconductor wafer is thicker than other nanosheets in the stack.

10. The method of claim 9, wherein the first nanosheet in the stack has a thickness of from about 20 nanometers to about 35 nanometers, and ranges therebetween.

11. The method of claim 9, wherein the other nanosheets in the stack have a thickness of from about 10 nanometers to about 25 nanometers, and ranges therebetween.

12. The method of claim 2, further comprising the step of:

filling the trenches with a trench oxide prior to oxidizing the top portion of the bulk semiconductor wafer.

13. The method of claim 1, wherein the oxidizing step comprises the step of:

annealing the bulk semiconductor wafer in an oxygen ambient under conditions sufficient to form the dielectric isolation region in the top portion of the bulk semiconductor wafer.

14. The method of claim 13, wherein the conditions comprise annealing the bulk semiconductor wafer at a temperature of from about 750°

C. to about 1,500°

C., and ranges therebetween.

15. The method of claim 13, wherein the conditions comprise annealing the bulk semiconductor wafer for a duration of from about 60 seconds to about 1 hour, and ranges therebetween.

16. A method of forming a nanowire field effect transistor (FET) device, the method comprising the steps of:

forming a plurality of nanosheets as a stack on a bulk semiconductor wafer, wherein the plurality of nanosheets comprises alternating layers of a sacrificial material and a channel material as the stack on the bulk semiconductor wafer;

patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks;

forming spacers covering sidewalls of the nanowire stacks;

oxidizing a top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer;

removing the spacers;

selectively removing portions of the layers of the sacrificial material from the nanowire stacks in a channel region of the FET device releasing portions of the channel material from the nanowire stacks, wherein the portions of the channel material released from the nanowire stacks form nanowire channels of the FET device; and

forming a gate surrounding the nanowire channels in the channel region of the device.

17. The method of claim 16, further comprising the step of:

implanting at least one dopant into the top portion of the bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer, and wherein the at least one dopant is selected from the group consisting of fluorine, phosphorous, and combinations thereof

18. The method of claim 17, further comprising the step of:

filling the trenches with a trench oxide prior to oxidizing the top portion of the bulk semiconductor wafer.

19. The method of claim 16, further comprising the steps of:

forming at least one dummy gate over the nanowire stacks in the channel region of the FET device;

forming dummy gate spacers on opposite sides of the dummy gate;

forming doped source and drain regions of the FET device;

burying the dummy gate in a gap fill dielectric material;

removing the dummy gate forming at least one gate trench in the gap fill dielectric; and

forming the gate in the gate trench.

20. A nanowire FET device, comprising:

a bulk semiconductor wafer comprising a dielectric isolation region in a top portion thereof, wherein the dielectric isolation region comprises a thermal oxide;

nanowire stacks on the bulk semiconductor wafer, wherein each of the nanowire stacks comprises alternating layers of a sacrificial material and a channel material, and wherein portions of the channel material are released from the nanowires stacks in a channel region of the FET device and comprise nanowire channels of the FET device; and

a gate surrounding the nanowire channels in the channel region of the device.

21. The nanowire FET device of claim 20, wherein the gate surrounds one or more of the nanowire channels in a gate-all-around configuration.