SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
First Claim
1. A method of fabricating a semiconductor device, comprising:
- forming a heterogeneous channel layer on a strain relaxed buffer (SRB) layer, the heterogeneous channel layer including a silicon layer on a first portion of the SRB layer and a silicon germanium (SiGe) alloy layer on a second portion of the SRB layer;
performing a first etching process on the heterogeneous channel layer and the SRB layer to form a plurality of first trenches and a plurality of second trenches, wherein each first trench penetrates through the silicon layer and into the first portion of the SRB layer to a first depth, and wherein each second trench penetrates through the SiGe alloy layer and into the second portion of the SRB layer to a second depth;
forming first liners on first sidewalls of the first trenches having the first depth and second sidewalls of the second trenches having the second depth; and
performing a second etching process on the SRB layer exposed by the first liners so that the first trenches are extended to a third depth to form a plurality of first fin type structures and the second trenches are extended to a fourth depth to form a plurality of second fin type structures, wherein the first fin type structures are defined by the first trenches having the third depth and the second fin type structures are defined by the second trenches having the fourth depth.
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Accused Products
Abstract
A method of fabricating a semiconductor device is provided as follows. A channel layer is formed on a strain relaxed buffer (SRB) layer. A first etching process is performed on the channel layer and the SRB layer to form a plurality of trenches. The trenches penetrate through the channel layer and into the SRB layer to a first depth. First liners are formed on first sidewalls of the trenches having the first depth. The first liners cover the first sidewalls. A second etching process is performed on the SRB layer exposed through the trenches. The second etching process is performed on the SRB layer using a gas etchant having etch selectivity with respect to the first liners so that after the performing of the second etching process, the first liners remain on the first sidewalls.
12 Citations
20 Claims
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1. A method of fabricating a semiconductor device, comprising:
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forming a heterogeneous channel layer on a strain relaxed buffer (SRB) layer, the heterogeneous channel layer including a silicon layer on a first portion of the SRB layer and a silicon germanium (SiGe) alloy layer on a second portion of the SRB layer; performing a first etching process on the heterogeneous channel layer and the SRB layer to form a plurality of first trenches and a plurality of second trenches, wherein each first trench penetrates through the silicon layer and into the first portion of the SRB layer to a first depth, and wherein each second trench penetrates through the SiGe alloy layer and into the second portion of the SRB layer to a second depth; forming first liners on first sidewalls of the first trenches having the first depth and second sidewalls of the second trenches having the second depth; and performing a second etching process on the SRB layer exposed by the first liners so that the first trenches are extended to a third depth to form a plurality of first fin type structures and the second trenches are extended to a fourth depth to form a plurality of second fin type structures, wherein the first fin type structures are defined by the first trenches having the third depth and the second fin type structures are defined by the second trenches having the fourth depth. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of fabricating a semiconductor device, comprising:
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forming a channel layer on a strain relaxed buffer (SRB) layer; performing a first etching process on the channel layer and the SRB layer to form a plurality of trenches, wherein the trenches penetrate through the channel layer and into the SRB layer to a first depth; forming first liners on first sidewalls of the trenches having the first depth, wherein the first liners cover the first sidewalls; and performing a second etching process on the SRB layer exposed through the trenches, wherein the second etching process is performed on the SRB layer using a gas etchant having etch selectivity with respect to the first liners so that after the performing of the second etching process, the first liners remain on the first sidewalls. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A semiconductor device, comprising:
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a first transistor and a second transistor disposed on a strain relaxed buffer (SRB) layer, wherein the SRB layer includes a first protrusion and a second protrusion and wherein the first protrusion and the second protrusion are protruded from an upper surface of the SRB layer; and a gate line connected to a first gate electrode of the first transistor and a second gate electrode of the second transistor, wherein the first transistor includes a silicon layer stacked on an upper surface of the first protrusion, wherein the second transistor includes a silicon germanium alloy layer stacked on the second protrusion, wherein a width of the first protrusion is greater than a width of the second silicon layer, the width of the first protrusion and the width of the second silicon layer being measured at a boundary between the first protrusion and the silicon layer, and wherein a width of the second protrusion is greater than a width of the silicon germanium alloy layer, the width of the second protrusion and the width of the silicon germanium alloy layer being measured at a boundary between the second protrusion and the silicon germanium alloy layer. - View Dependent Claims (20)
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Specification