SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

• US 20170117414A1
• Filed: 11/16/2015
• Published: 04/27/2017
• Est. Priority Date: 10/26/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Huang, Shih-Hsien, Chen, Chien-Hung, Wu, Chun-Yuan, Wu, Tien-I, Yang, Yu-Ru, Chiang, Huai-Tzu, Chen, Kun-Hsin
• Granted Patent: US 10,497,797 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 2924/13067 FinFET, source/drain region shapes fins on the silicon surface

Abstract

A semiconductor structure including a semiconductor substrate and at least a fin structure formed thereon. The semiconductor substrate includes a first semiconductor material. The fin structure includes a first epitaxial layer and a second epitaxial layer formed between the first epitaxial layer and the semiconductor substrate. The first epitaxial layer includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The second epitaxial layer includes the first semiconductor material and the second semiconductor material. The second epitaxial layer further includes conductive dopants.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate comprising a first semiconductor material; and

at least a fin formed on the semiconductor substrate, the fin comprising;

a first epitaxial layer comprising the first semiconductor material and a second semiconductor material, a lattice constant of the second semiconductor material being different from a lattice constant of the first semiconductor material; and

a second epitaxial layer formed between the first epitaxial layer and the semiconductor substrate, the second epitaxial layer comprising the first semiconductor material and the second semiconductor material, and the second epitaxial layer further comprising conductive dopants.

2. The semiconductor structure according to claim 1, wherein the second semiconductor material in the first epitaxial layer comprises a first concentration, the second semiconductor material in the second epitaxial layer comprises a second concentration, and the second concentration is equal to or smaller than the first concentration.

3. The semiconductor structure according to claim 1, further comprising a gate layer formed on the fin, and the gate layer comprises a first conductivity type.

4. The semiconductor structure according to claim 3, wherein the conductive dopants in the second epitaxial layer comprises a second conductivity type complementary to the first conductivity type.

5. The semiconductor structure according to claim 4, wherein the first conductivity type is an n type, and the conductive dopants comprise boron (B).

6. The semiconductor structure according to claim 4, wherein the first conductivity type is a p type, and the conductive dopants comprise phosphorous (P) or arsenic (As).

7. The semiconductor structure according to claim 1, wherein the conductive dopants in the second epitaxial layer comprises a concentration, and the concentration is smaller than 1E19/cm³.

8. The semiconductor structure according to claim 1, wherein the fin further comprises a third epitaxial layer, the third epitaxial layer comprises the first semiconductor material and the second semiconductor material, and the second epitaxial layer is sandwiched in between the first epitaxial layer and the third epitaxial layer.

9. The semiconductor structure according to claim 8, wherein the second semiconductor material in the first epitaxial layer comprises a first concentration, the second semiconductor material in the second epitaxial layer comprises a second concentration, the second semiconductor material in the third epitaxial layer comprises a third concentration, the second concentration is equal to or larger than the third concentration, and the first concentration is equal to or larger than the second concentration.

10. The semiconductor structure according to claim 8, wherein a thickness of the second epitaxial layer is smaller than a thickness of the first epitaxial layer and a thickness of the third epitaxial layer.

11. A method for manufacturing a semiconductor structure, comprising:

providing a semiconductor substrate comprising a first semiconductor material, a dielectric structure being formed on the semiconductor substrate, and the dielectric structure having a recess formed therein;

forming a second epitaxial layer in the recess, the second epitaxial layer comprising the first semiconductor material and a second semiconductor material, a lattice constant of the second semiconductor material being different from a lattice constant of the first semiconductor material, and the second epitaxial layer comprising conductive dopants;

forming a first epitaxial layer on the second epitaxial layer, the first epitaxial layer comprising the first semiconductor material and the second semiconductor material, and the first epitaxial layer being an undoped epitaxial layer; and

removing a portion of dielectric structure to form a fin on the semiconductor substrate.

12. The method for manufacturing the semiconductor structure according to claim 11, wherein a bottom of the recess is coplanar with or lower than a bottom of the dielectric structure.

13. The method for manufacturing the semiconductor structure according to claim 11, further comprising forming a third epitaxial layer before forming the second epitaxial layer, the third epitaxial layer comprising an undoped epitaxial layer, and the third epitaxial layer comprising the first semiconductor material and the second semiconductor material.

14. The method for manufacturing the semiconductor structure according to claim 13, wherein the second semiconductor material in the first epitaxial layer comprise a first concentration, the second semiconductor material in the second epitaxial layer comprises a second concentration, and the second semiconductor material in the third epitaxial layer comprises a third concentration.

15. The method for manufacturing the semiconductor structure according to claim 14, wherein the second concentration is equal to or larger than the third concentration, and the first concentration is equal to or larger than the second concentration.

16. The method for manufacturing the semiconductor structure according to claim 13, wherein the recess comprises a depth, the first epitaxial layer comprises a first thickness and the first thickness is one-third to a half of the depth of the recess, the second epitaxial layer comprises a second thickness and the second thickness is one-tenth of the depth of the recess, and the third epitaxial layer comprises a third thickness and the third thickness is one-third to a half of the depth of the recess.

17. The method for manufacturing the semiconductor structure according to claim 13, further comprising performing a thermal treatment after forming the third epitaxial layer and before forming the second epitaxial layer.

18. The method for manufacturing the semiconductor structure according to claim 13, further comprising forming a fourth epitaxial layer in the recess before forming the third epitaxial layer, and the fourth epitaxial layer comprising the first semiconductor material.

19. The method for manufacturing the semiconductor structure according to claim 13, wherein the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are in-situ formed.

20. The method for manufacturing the semiconductor structure according to claim 11, further comprising performing a thermal treatment after forming the second epitaxial layer.

21. The method for manufacturing the semiconductor structure according to claim 11, further comprising forming a gate layer on the fin, and the gate layer comprising a first conductivity type.

22. The method for manufacturing the semiconductor structure according to claim 21, wherein the conductive dopants in the second epitaxial layer comprise a second conductivity type complementary to the first conductivity type.