FREQUENCY SYNTHESIZER WITH INJECTION LOCKED OSCILLATOR

• US 20170117907A1
• Filed: 04/08/2015
• Published: 04/27/2017
• Est. Priority Date: 04/08/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: GROLLITSCH, Werner
• Granted Patent: US 9,998,128 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H03L 7/22 using more than one loop
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

Representative implementations of devices and techniques provide reduced jitter for a controlled oscillator. An edge of a reference signal is injected at various points within the oscillator, and is replaced for an edge of the generated oscillation signal at the injection point.

Claims

1. A ring oscillator circuit, comprising:

a plurality of inverters; and

a plurality of multiplexers, a multiplexer coupled to an output of each inverter at a first input of the multiplexer and an inverter coupled to an output of each multiplexer at an input of the inverter,

each multiplexer arranged to receive a reference signal at a second input of the multiplexer and to output the reference signal when an enable signal received at the multiplexer is in a first state and to output an oscillation signal received at the first input of the multiplexer when the enable signal is in a second state.

2. The ring oscillator circuit of claim 1, wherein the plurality of inverters and the plurality of multiplexers are arranged in a loop and generate the oscillation signal, and wherein the loop is opened at periodic intervals and an edge of the reference signal replaces an edge of the oscillation signal at the intervals.

3. The ring oscillator circuit of claim 2, wherein the replacement of the edge of the reference signal for the edge of the oscillation signal adjusts a timing of the oscillation signal.

4. The ring oscillator circuit of claim 1, wherein the reference signal comprises a periodic pulse signal having a rising edge and a falling edge on each pulse, one of the rising edge or the falling edge replacing an edge of the oscillation signal at an output of a multiplexer when the enable signal received at the multiplexer is in the first state.

5. The ring oscillator circuit of claim 1, wherein an enable signal at a first multiplexer of the plurality of multiplexers and an enable signal at a second multiplexer of the plurality of multiplexers are not in the first state simultaneously.

6. The ring oscillator circuit of claim 1, wherein at least one enable signal received at a multiplexer is activated to the first state at every cycle of the reference signal.

7. The ring oscillator circuit of claim 1, wherein the multiplexers of the plurality of multiplexers are subsequently enabled at a frequency comprising a combination of an integer multiplication factor and a fractional multiplication factor of a frequency of the reference signal.

8. The ring oscillator circuit of claim 7, wherein the multiplexers of the plurality of multiplexers are enabled in an order that is not sequential to an order of their electrical coupling within the circuit.

9. A phase-locked loop (PLL) system, comprising:

a multi-stage ring oscillator circuit, including a plurality of inverters and a plurality of multiplexers alternately coupled in a loop, a multiplexer coupled to an output of each inverter at a first input of the multiplexer and an inverter coupled to an output of each multiplexer at an input of the inverter; and

a digital control module arranged to enable each of the plurality of multiplexers via an enable signal according to a predetermined pattern, each multiplexer arranged to receive a reference signal at a second input of the multiplexer and to output the reference signal when the enable signal received at the multiplexer is in a first state and to output an oscillation signal received at the first input of the multiplexer when the enable signal is in a second state.

10. The PLL system of claim 10, further comprising a plurality of phase detectors, a phase detector coupled to the output of each inverter and to the reference signal and arranged to detect a phase difference between the oscillation signal and the reference signal and to feed back a difference signal to the digital control module based on the detecting.

11. The PLL system of claim 10, further comprising a cycle counter coupled to an output of one of the multiplexers and arranged to count a quantity of cycles of the multi-stage ring oscillator circuit and to output a result signal to the digital control module based on the counting.

12. The PLL system of claim 10, further comprising a loop filter arranged to receive an aggregate signal including a frequency control signal and feedback from the multi-stage ring oscillator circuit and to tune a frequency of the multi-stage ring oscillator circuit based on the aggregate signal.

13. The PLL system of claim 12, wherein the frequency control signal comprises an accumulated signal based on a frequency control word and the feedback includes a phase error between the oscillation signal and the reference signal, and wherein the aggregate signal includes the phase error subtracted from the frequency control signal.

14. The PLL system of claim 10, further comprising an injection controller arranged to determine which phase of the multi-stage ring oscillator circuit to enable a multiplexer of the plurality of multiplexers via the enable signal according to the predetermined pattern.

15. The PLL system of claim 10, wherein the digital control module is comprised of digital components clocked via the reference signal.

16. The PLL system of claim 10, wherein the multi-stage ring oscillator circuit comprises a digitally controlled ring oscillator (DCRO) and includes a tuning matrix of inverter stages coupled in parallel to the plurality of inverters to drive a frequency of the multi-stage ring oscillator circuit to a desired frequency value.

17. The PLL system of claim 10, wherein the multi-stage ring oscillator circuit comprises an analog voltage controlled oscillator (VCO).

18. A method, comprising:

alternately coupling a plurality of inverters and a plurality of multiplexers in a loop, such that a multiplexer is coupled to an output of each inverter at a first input of the multiplexer and an inverter is coupled to an output of each multiplexer at an input of the inverter;

receiving a reference signal at a second input of each of the plurality of multiplexers;

outputting, from a multiplexer, the reference signal when an enable signal received at the multiplexer is in a first state; and

outputting, from the multiplexer, an oscillation signal received at the first input of the multiplexer when the enable signal is in a second state.

19. The method of claim 18, further comprising independently enabling each multiplexer of the plurality of multiplexers via the enable signal according to a predetermined frequency comprising a combination of an integer multiplication factor and a fractional multiplication factor of a frequency of the reference signal.

20. The method of claim 19, further comprising generating the oscillation signal via the plurality of inverters and the plurality of multiplexers in the loop, and reducing jitter of the oscillation signal by opening the loop and replacing an edge of the oscillation signal by an edge of the reference signal according to the predetermined frequency.

21. The method of claim 19, further comprising generating the oscillation signal via the plurality of inverters and the plurality of multiplexers in the loop, and adjusting a resolution of a frequency of the oscillation signal by adjusting the predetermined frequency and opening the loop and replacing an edge of the oscillation signal by an edge of the reference signal according to the adjusted predetermined frequency.

22. The method of claim 19, further comprising generating the oscillation signal via the plurality of inverters and the plurality of multiplexers in the loop, and adjusting a resolution of a frequency of the oscillation signal by opening the loop and replacing a rising and/or falling edge of the oscillation signal by a rising and/or a falling edge of the reference signal according to a predetermined combination.

23. The method of claim 18, further comprising acquiring an oscillation frequency, including:

evaluating a phase difference between the reference signal and the oscillation signal;

sampling a cycle counter clocked by the oscillation signal at a frequency of the reference signal to represent frequency information of the phase difference;

subtracting the frequency information of the phase difference from an accumulated frequency control word signal to determine an aggregate phase error signal; and

tuning a frequency of the oscillation signal based on the aggregate signal.

24. The method of claim 23, further comprising monitoring for a lock indication based on the phase difference and locking a phase-locked loop (PLL) when the phase difference is less than a predetermined threshold.

25. The method of claim 18, further comprising locking injection, including:

determining a phase of the oscillation signal for injection of an edge of the reference signal;

evaluating a phase difference between the oscillation signal and the reference signal;

driving the oscillation signal to a higher frequency when the edge of the reference signal leads a corresponding edge of the oscillation signal; and

driving the oscillation signal to a lower frequency when the edge of the reference signal lags a corresponding edge of the oscillation signal.

26. The method of claim 25, further comprising evaluating an accumulated value of at least a portion of a frequency control word and tuning a frequency of the oscillation signal based on the accumulated value and the phase difference.

27. A phase-locked loop (PLL) system, comprising:

a multi-stage ring oscillator circuit, including a quantity of inverters and a same quantity of multiplexers alternately coupled in a loop, a multiplexer coupled to an output of each inverter at a first input of the multiplexer and an inverter coupled to an output of each multiplexer at an input of the inverter, the multi-stage ring oscillator circuit arranged to generate an output of the PLL system comprising an oscillation signal; and

a digital control module arranged to tune a frequency of the multi-stage ring oscillator circuit based on an aggregated control word, to determine a phase of the oscillation signal for injection of an edge of a reference signal, and to enable a multiplexer to insert the edge of the reference signal in place of a corresponding edge of the oscillation signal according to a predetermined pattern.