METHOD AND SYSTEM FOR PROGRAMMING A MULTI-LAYER NON-VOLATILE MEMORY HAVING A SINGLE FOLD DATA PATH

• US 20170123664A1
• Filed: 10/30/2015
• Published: 05/04/2017
• Est. Priority Date: 10/30/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Parker, Liam Michael, Bennett, Alan David, Sinclair, Alan Welsh, Gorobets, Sergey Anatolievich
• Granted Patent: US 10,042,553 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A method is disclosed for only permitting data from a host to be written to a first non-volatile memory layer and only permitting data to be written into a second non-volatile memory layer via a maintenance operation over a single data path between the layers. The single data path may be an on-chip copy data path. A memory system includes a multi-layer non-volatile memory and data management circuitry, where the data management circuitry includes data flow path circuitry defining only a single data path for programming any data into the second layer. Maintenance manager circuitry and programming interleave circuitry in the data management circuitry are configured to select a maintenance schedule, and to interleave programming of host data with maintenance operation writes for the selected maintenance schedule only along the one or more data paths defined by the data flow path circuitry.

Claims

1. A method of managing data comprising:

performing, in a non-volatile memory system having a non-volatile memory with a plurality of layers and a controller in communication with the at least one non-volatile memory, each of the plurality of layers having a different bit-per-cell data capacity, the following steps;

only directing data received from a host to a first of the plurality of layers;

prior to programming the data received from the host into the first layer, determining whether a maintenance operation is necessary for the first layer; and

in response to determining that the maintenance operation is necessary for the first layer;

selecting a maintenance cycle type from a predetermined set of maintenance cycle types for the non-volatile memory based on a status of the first layer; and

when the selected maintenance cycle type includes instructions to transfer data from the first layer to a second layer of the plurality of layers, executing the selected maintenance cycle type by transferring valid data from the first layer to a single open block in the second layer, wherein the non-volatile memory system only assigns a new open block in the second layer for receiving data from the first layer after the single open block is fully programmed.

2. The method of claim 1, wherein determining that the maintenance operation is necessary comprises determining that an amount of free space in the first layer is less than a predetermined maintenance threshold.

3. The method of claim 2, wherein the status of the first layer comprises an amount of valid data in the first layer, and wherein selecting the maintenance cycle type comprises selecting a maintenance cycle type that includes instructions to transfer data from the first layer to the second layer when the amount of valid data in the first layer is greater than or equal to a data transfer threshold.

4. The method of claim 1, further comprising relocating valid data from at least one closed block in the second layer to an open block in the first layer when an amount of free space in the second layer is less than or equal to a relocation threshold.

5. The method of claim 1, wherein the first layer comprises a lower bit-per-cell-capacity than the second layer and wherein transferring valid data from the first layer to the single open block in the second layer comprises transferring the valid data from the first layer to the single open block via an on-chip copy process.

6. The method of claim 3, wherein the selected maintenance cycle type comprises a combination of instructions for programming data received from the host into the first layer and transferring data from at least one source block in the first layer to the single open block in the second layer.

7. The method of claim 6, further comprising determining an interleave ratio for interleaving the programming of data received from the host and transferring data from the at least one source block, prior to executing the selected maintenance cycle, based on an amount of valid data in the at least one source block.

8. A memory system, comprising:

at least one non-volatile memory having a first layer and a second layer of non-volatile memory cells, wherein the first layer has only non-volatile memory cells configured at a first bit-per-cell capacity and the second layer has only non-volatile memory cells configured at a second bit-per-cell capacity that is greater than the first bit-per-cell capacity; and

data management circuitry in communication with the at least one non-volatile memory, wherein the data management circuitry comprises;

data flow path circuitry defining a plurality of predetermined data paths for programming data received from a host or maintenance operation data into the first layer, and defining only a single data path for programming any data into the second layer;

maintenance manager circuitry configured to select a foreground maintenance schedule to free space in at least one of the first and second layers based on a status of at least one of the first and second layers; and

program interleaving circuitry configured to interleave programming of data received from the host with maintenance operation writes for the foreground maintenance schedule selected by the maintenance manager circuitry along one or more data paths defined by the data flow path circuitry.

9. The memory system of claim 8, wherein the single data path for programming any data into the second layer comprises a data path between the first layer and the second layer.

10. The memory system of claim 9, wherein the single data path comprises an on-chip copy data path configured to copy data from the first layer to the second layer, wherein the data management circuitry is configured to only permit programming of data to the second layer via the single data path.

11. The memory system of claim 8, wherein the first layer comprises a plurality of open blocks of memory cells, each of the plurality of open blocks being configured to receive data of a different data type from the host.

12. The memory system of claim 11, wherein the first layer further comprises at least one open maintenance data block configured to only receive valid data relocated from a closed block in the first layer, and at least one open maintenance block configured to only receive valid data relocated from the second layer.

13. The memory system of claim 12, wherein the plurality of open blocks comprises a random host data update block and a sequential host data update block.

14. The memory system of claim 8, wherein the non-volatile memory comprises a silicon substrate and a plurality of memory cells forming a monolithic three-dimensional structure, wherein at least one portion of the memory cells is vertically disposed with respect to the silicon substrate.

15. The memory system of claim 8, wherein the at least one non-volatile memory comprises a plurality of non-volatile memory die, and wherein the data management circuitry is configured to first select an available non-volatile memory die for programming data received from the host prior to selecting the maintenance cycle type.

17. The memory system of claim 8, wherein the controller is configured to only maintain one open maintenance block in the second layer and to only assign a new maintenance block in the second layer after fully programming the one open maintenance block.

18. The memory system of claim 17, wherein the first layer comprises a one bit-per-cell capacity and the second layer comprises a three bit-per-cell capacity.

19. The memory system of claim 18, wherein the at least one non-volatile memory comprises a plurality of non-volatile memory die, and wherein the controller is configured to first select an available non-volatile memory die for programming data received from the host prior to selecting the maintenance cycle type.

20. The memory system of claim 19, wherein the controller is configured to, in response to determining that the second layer has less free space than a foreground maintenance threshold, relocate valid data from a closed block in the second layer to at least one relocation destination block in the first layer.

16. A memory system, comprising:

at least one non-volatile memory having a first layer and a second layer of non-volatile memory cells, wherein the first layer has only non-volatile memory cells configured at a first bit-per-cell capacity and the second layer has only non-volatile memory cells configured at a second bit-per-cell capacity that is greater than the first bit-per-cell capacity; and

a controller in communication with the at least one non-volatile memory, wherein the controller is configured to;

identify a type of data received from a host and determine whether a maintenance operation is necessary in the first layer before programming the received data;

select a maintenance cycle type from a predetermined set of maintenance cycle types for the non-volatile memory based on a status of the first layer;

when the selected maintenance cycle type includes instructions to move data to the second layer, interleave programming of an amount of the received data into the first layer with re-programming of valid data from a closed block in the first layer to the second layer; and

only direct data received from the host to the first layer and to only permit programming of data into an open maintenance block in the second layer from the first layer via an on-chip copy operation.