WRITE MAPPING TO MITIGATE HARD ERRORS VIA SOFT-DECISION DECODING

• US 20170123891A1
• Filed: 01/17/2017
• Published: 05/04/2017
• Est. Priority Date: 06/23/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Alhussien, AbdelHakim S., Haratsch, Erich F., Cohen, Earl T., Wu, Yunxiang
• Granted Patent: US 9,990,247 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence
• CPC Class Codes: H03M 13/458 by updating bit probabilities or hard decisions in an iterative fashion for convergence to a final decoding result

Abstract

An apparatus includes an interface and a control circuit. The interface may be configured to process read/write operations to/from a memory. The control circuit may be configured to create dependencies between a current bit in a sequence of data bits and neighboring bits in the sequence of data bits to generate mapped bits in response to a condition in a region of the memory being true, write the mapped bits among at least two memory cells in the region of the memory with at least two of the mapped bits stored in each of the memory cells, where the dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.

Claims

1. An apparatus comprising:

an interface configured to process a plurality of read/write operations to/from a memory; and

a control circuit configured to create a plurality of dependencies between a current bit in a sequence of data bits and a plurality of neighboring bits in the sequence of data bits to generate a plurality of mapped bits in response to a condition in a region of the memory being true, write the plurality of mapped bits among at least two cells of a plurality of memory cells in the region of the memory with at least two of the plurality of mapped bits stored in each of the plurality of memory cells, wherein the plurality of dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.

2. The apparatus according to claim 1, wherein the region is one of a codeword, a page, or a block.

3. The apparatus according to claim 1, wherein the control circuit is further configured to read a lower page of a multi-level-cell page in the region, and the condition is based on read noise in a least-significant bit of the lower page.

4. The apparatus according to claim 1, wherein the control circuit is further configured to detect at least one bit-line defect in the region, and the condition is based on the detection.

5. The apparatus according to claim 1, wherein the control circuit is further configured to read a plurality of single-level-cell pages in the region and compact the plurality of single-level-cell pages into a triple-level cell page, and the condition is based on read noise in the plurality of single-level-cell pages.

6. The apparatus according to claim 1, wherein the control circuit is further configured to determine that a read voltage window of the region is insufficiently wide to capture errors without saturating log-likelihood ratio values, and the condition is based on the determination.

7. The apparatus according to claim 1, wherein the condition is based on a code rate assigned to the region.

8. The apparatus according to claim 1, wherein the control circuit is further configured to measure a number of stuck memory cells in the region, and the condition is based on the number of stuck memory cells.

9. The apparatus according to claim 1, wherein the interface and the control circuit form part of a solid-state drive controller.

10. A method for mitigating hard errors, comprising the steps of:

creating a plurality of dependencies between a current bit in a sequence of data bits and a plurality of neighboring bits in the sequence of data bits to generate a plurality of mapped bits in response to a condition in a region of a memory being true;

writing the plurality of mapped bits among at least two cells of a plurality of memory cells in the region of the memory with at least two of the plurality of mapped bits stored in each of the plurality of memory cells, wherein the plurality of dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state; and

writing the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.

11. The method according to claim 10, wherein the region is one of a codeword, a page, or a block.

12. The method according to claim 10, further comprising the step of:

reading a lower page of a multi-level-cell page in the region, wherein the condition is based on read noise in a least-significant bit of the lower page.

13. The method according to claim 10, further comprising the step of:

detecting at least one bit-line defect in the region, wherein the condition is based on the detection.

14. The method according to claim 10, further comprising the steps of:

reading a plurality of single-level-cell pages in the region; and

compacting the plurality of single-level-cell pages into a triple-level cell page, wherein the condition is based on read noise in the plurality of single-level-cell pages.

15. The method according to claim 10, further comprising the steps of:

determining that a read voltage window of the region is insufficiently wide to capture errors without saturating log-likelihood ratio values, wherein the condition is based on the determination.

16. The method according to claim 10, wherein the condition is based on a code rate assigned to the region.

17. The method according to claim 10, further comprising the step of:

measuring a number of stuck memory cells in the region, wherein the condition is based on the number of stuck memory cells.

18. The method according to claim 10, wherein the steps are performed in a solid-state drive controller.

19. An apparatus comprising:

a memory configured to store data; and

a controller configured to create a plurality of dependencies between a current bit in a sequence of data bits and a plurality of neighboring bits in the sequence of data bits to generate a plurality of mapped bits in response to a condition in a region of the memory being true, write the plurality of mapped bits among at least two cells of a plurality of memory cells in the region of the memory with at least two of the plurality of mapped bits stored in each of the plurality of memory cells, wherein the plurality of dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.

20. The apparatus according to claim 19, wherein the memory and the controller form part of a solid-state drive controller.