Systems and Methods for Efficient Soft Data Based Flash Memory Data Recovery

• US 20170123899A1
• Filed: 10/28/2015
• Published: 05/04/2017
• Est. Priority Date: 10/28/2015
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Zhao, Zhijun, Yang, Shaohua, Krachkovsky, Victor
• Granted Patent: US 10,108,489 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/6325 Error control coding in combination with demodulation
• CPC Class Codes: H03M 13/6588 Compression or short representation of variables
• CPC Class Codes: H03M 5/02 Conversion to or from representation by pulses
• CPC Class Codes: H03M 7/00 Conversion of a code where information is represented by a given sequence or number of digits to a code where the same , similar or subset of information is represented by a different sequence or number of digits

Abstract

Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.

Claims

1. A system for accessing a flash memory device, the system comprising:

a data read circuit operable to compare voltages read from a set of M groups of N flash memory cells with a first threshold value to yield a binary output set, wherein the binary output set includes a set of M groups of N binary values, and wherein M and N are integers;

a first data decoding circuit operable to generate at least a first set of M soft data values each corresponding to a respective one of the M groups of N binary values; and

a second data decoding circuit operable to decode the first set of M soft data values to yield a data output.

2. The system of claim 1, wherein the first set of M soft data values corresponds to a low density parity check codeword, and wherein the second data decoding circuit is a low density parity check decoding circuit.

3. The system of claim 1, wherein the binary output set is a first binary output set;

wherein the data read circuit is further operable to compare voltages read from the set of M groups of N flash memory cells with a second threshold value to yield a second binary output set; and

wherein the first data decoding circuit is further operable to;

generate at least a second set of M soft data values each corresponding to a respective one of the M groups of N binary values, and a third set of M soft data values each corresponding to a respective one of the M groups of N binary values.

4. The system of claim 3, wherein the data output is a first data output, and wherein the second data decoding circuit is further operable to:

decode the second set of M soft data values to yield a second data output, and

decode the third set of M soft data values to yield a third data output.

5. The system of claim 1, wherein the binary output set is a first binary output set;

wherein the data read circuit is further operable to compare voltages read from the set of M groups of N flash memory cells with a second threshold value to yield a second binary output set, and to compare voltages read from the set of M groups of N flash memory cells with a third threshold value to yield a third binary output set; and

wherein the first data decoding circuit is further operable to;

generate at least a second set of M soft data values each corresponding to a respective one of the M groups of N binary values based upon the second binary output set, and a third set of M soft data values each corresponding to a respective one of the M groups of N binary values based upon the second binary output set; and

generate at least a fourth set of M soft data values each corresponding to a respective one of the M groups of N binary values based upon the third binary output set, and a fifth set of M soft data values each corresponding to a respective one of the M groups of N binary values based upon the second binary output set.

6. The system of claim 5, wherein the first set of M soft data values corresponds to a first low density parity check codeword, the second set of M soft data values corresponds to a second low density parity check codeword, the third set of M soft data values corresponds to a third low density parity check codeword, the fourth set of M soft data values corresponds to a fourth low density parity check codeword, and the fifth set of M soft data values corresponds to a fifth low density parity check codeword.

7. The system of claim 6, wherein N is three.

8. The system of claim 7, wherein M is 4096.

9. The system of claim 5, wherein the first data decoding circuit comprises:

a first look-up table including soft data values corresponding to the first binary output set generated based upon the first threshold;

a second look-up table including soft data values corresponding to the second binary output set generated based upon the second threshold; and

a third look-up table including soft data values corresponding to the third binary output set generated based upon the third threshold.

10. The system of claim 1, wherein the system is implemented as part of an integrated circuit.

11. The system of claim 1, wherein the system further comprises:

a first encoder circuit operable to apply a first encoding algorithm to a user data set to yield a number of the encoded codewords, wherein each of the number of encoded codewords includes M elements;

a second encoder circuit operable to apply a second encoding algorithm to a combination of the first number of the encoded codewords to yield M sets of N voltage values;

wherein each of the M sets of N voltage values represents corresponding elements of each of the number of the encoded codewords; and

a write circuit operable to apply voltages indicated by each of the N voltage levels to respective ones of the flash memory cells.

12. A method for accessing a solid state memory device, the method comprising:

accessing a set of M groups of N flash memory cells to yield M sets of N voltages, wherein M and N are integers;

comparing the M sets of N voltages with a first threshold value to yield M sets of N binary outputs;

using a first data decoding circuit to generate at least a first set of M soft data values each corresponding to a respective one of the M sets of N binary outputs; and

using a second data decoding circuit to decode the first set of M soft data values to yield a data output.

13. The method of claim 12, wherein the M sets of N binary outputs is a first group of M sets of N binary outputs;

wherein the data output is a first data output; and

wherein the method further comprises;

comparing the M sets of N voltages with a second threshold value to yield a second group of M sets of N binary outputs;

using the first data decoding circuit to generate a second set of M soft data values and a third set of M soft data values where each of the M soft data values corresponds to a respective one of the M sets of N binary outputs in the second group of M sets of N binary outputs; and

using the second data decoding circuit to;

decode the second set of M soft data values to yield a second data output, and

decode the third set of M soft data values to yield a third data output.

14. The method of claim 12, wherein the M sets of N binary outputs is a first group of M sets of N binary outputs;

wherein the data output is a first data output; and

wherein the method further comprises;

comparing the M sets of N voltages with a second threshold value to yield a second group of M sets of N binary outputs;

comparing the M sets of N voltages with a third threshold value to yield a third group of M sets of N binary outputs;

using the first data decoding circuit to;

generate a second set of M soft data values and a third set of M soft data values where each of the M soft data values corresponds to a respective one of the M sets of N binary outputs in the second group of M sets of N binary outputs; and

generate a fourth set of M soft data values and a fifth set of M soft data values where each of the M soft data values corresponds to a respective one of the M sets of N binary outputs in the third group of M sets of N binary outputs; and

using the second data decoding circuit to;

decode the second set of M soft data values to yield a second data output;

decode the third set of M soft data values to yield a third data output;

decode the fourth set of M soft data values to yield a fourth data output; and

decode the fifth set of M soft data values to yield a fifth data output.

15. The method of claim 14, wherein the first data decoding circuit comprises:

a first look-up table including soft data values corresponding to the first group of M sets of N binary outputs generated based upon the first threshold;

a second look-up table including soft data values corresponding to the second group of M sets of N binary outputs generated based upon the second threshold; and

a third look-up table including soft data values corresponding to the third group of M sets of N binary outputs generated based upon the third threshold.

16. The method of claim 14, wherein the second data decoding circuit is a low density parity check decoding circuit.

17. The method of claim 16, wherein the first set of M soft data values corresponds to a first low density parity check codeword, the second set of M soft data values corresponds to a second low density parity check codeword, the third set of M soft data values corresponds to a third low density parity check codeword, the fourth set of M soft data values corresponds to a fourth low density parity check codeword, and the fifth set of M soft data values corresponds to a fifth low density parity check codeword.

18. The method of claim 12, wherein N is three.

19. The method of claim 12, wherein M is 4096.

20. A flash memory access system, the system comprising:

a plurality of flash memory cells;

a first encoder circuit operable to apply a low density parity check encoding algorithm to a user data set to yield a number of the low density parity check codewords, wherein each of the number of low density parity check codewords includes M elements, and wherein M is an integer;

a second encoder circuit operable to apply a second encoding algorithm to a combination of the first number of the low density parity check codewords to yield M sets of N voltage values, wherein each of the M sets of N voltage values represents corresponding elements of each of the number of the low density parity check codewords, and wherein N is an integer; and

a write circuit operable to apply voltages indicated by each of the N voltage levels to respective ones of a subset of the flash memory cells;

a data read circuit operable to compare voltages read from a set of M groups of N flash memory cells with a first threshold value to yield a binary output set, wherein the binary output set includes a set of M groups of N binary values, and wherein M and N are integers;

a first data decoding circuit operable to generate at least a first set of M soft data values each corresponding to a respective one of the M groups of N binary values;

a second data decoding circuit operable to decode the first set of M soft data values to yield a data output.