Systems and Methods for Efficient Soft Data Based Flash Memory Data Recovery
First Claim
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1. A system for accessing a flash memory device, the system comprising:
- a data read circuit operable to compare voltages read from a set of M groups of N flash memory cells with a first threshold value to yield a binary output set, wherein the binary output set includes a set of M groups of N binary values, and wherein M and N are integers;
a first data decoding circuit operable to generate at least a first set of M soft data values each corresponding to a respective one of the M groups of N binary values; and
a second data decoding circuit operable to decode the first set of M soft data values to yield a data output.
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Abstract
Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.
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Citations
20 Claims
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1. A system for accessing a flash memory device, the system comprising:
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a data read circuit operable to compare voltages read from a set of M groups of N flash memory cells with a first threshold value to yield a binary output set, wherein the binary output set includes a set of M groups of N binary values, and wherein M and N are integers; a first data decoding circuit operable to generate at least a first set of M soft data values each corresponding to a respective one of the M groups of N binary values; and a second data decoding circuit operable to decode the first set of M soft data values to yield a data output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for accessing a solid state memory device, the method comprising:
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accessing a set of M groups of N flash memory cells to yield M sets of N voltages, wherein M and N are integers; comparing the M sets of N voltages with a first threshold value to yield M sets of N binary outputs; using a first data decoding circuit to generate at least a first set of M soft data values each corresponding to a respective one of the M sets of N binary outputs; and using a second data decoding circuit to decode the first set of M soft data values to yield a data output. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A flash memory access system, the system comprising:
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a plurality of flash memory cells; a first encoder circuit operable to apply a low density parity check encoding algorithm to a user data set to yield a number of the low density parity check codewords, wherein each of the number of low density parity check codewords includes M elements, and wherein M is an integer; a second encoder circuit operable to apply a second encoding algorithm to a combination of the first number of the low density parity check codewords to yield M sets of N voltage values, wherein each of the M sets of N voltage values represents corresponding elements of each of the number of the low density parity check codewords, and wherein N is an integer; and a write circuit operable to apply voltages indicated by each of the N voltage levels to respective ones of a subset of the flash memory cells; a data read circuit operable to compare voltages read from a set of M groups of N flash memory cells with a first threshold value to yield a binary output set, wherein the binary output set includes a set of M groups of N binary values, and wherein M and N are integers; a first data decoding circuit operable to generate at least a first set of M soft data values each corresponding to a respective one of the M groups of N binary values; a second data decoding circuit operable to decode the first set of M soft data values to yield a data output.
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Specification