SHIFT REGISTER

• US 20170124971A1
• Filed: 04/27/2016
• Published: 05/04/2017
• Est. Priority Date: 10/29/2015
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Tu, Chun-Da, Chen, Yung-Chih, Huang, Cheng-Han, Hong, Kai-Wei, Chang, Hsiang-Sheng, Yang, Chuang-Cheng
• Granted Patent: US 10,019,956 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register including a voltage set unit, a driver unit, a control unit, a first transistor, a second transistor, a third transistor and a fourth transistor is provided. The voltage set unit provides a terminal voltage. The driver unit provides a main gate signal according to the terminal voltage and a clock signal. The control unit provides a control signal. The first transistor receives the terminal voltage, a level reference voltage and the control signal. The second transistor is coupled to the first transistor and receives a low voltage and the control signal. The third transistor receives the terminal voltage, a level reference voltage and a gate reference signal. The fourth transistor is coupled to the third transistor and receives the low voltage and the gate reference signal.

Claims

1. A shift register, comprising:

a voltage setting unit configured to receive a first gate reference signal so as to provide a terminal voltage;

a drive unit configured to receive the terminal voltage and a clock signal, so as to provide a main gate signal according to the terminal voltage and the clock signal;

a first control unit configured to receive a first latch reference signal, the terminal voltage and a first low voltage, so as to provide a first control signal;

a first transistor having a first end configured to receive the terminal voltage, a second end configured to receive a level reference signal, and a control end configured to receive the first control signal;

a second transistor having a first end coupled to the second end of the first transistor, a second end configured to receive a second low voltage, and a control end configured to receive the first control signal;

a third transistor having a first end configured to receive the terminal voltage, a second end configured to receive the level reference signal, and a control end configured to receive a second gate reference signal; and

a fourth transistor having a first end coupled to the second end of the third transistor, a second end configured to receive the second low voltage, and a control end configured to receive the second gate reference signal.

2. The shift register according to claim 1, wherein the level reference signal is the main gate signal, the first low voltage is equal to the second low voltage, and the first latch reference signal is a gate high voltage.

3. The shift register according to claim 1, wherein an enable time of the first gate reference signal is earlier than an enable time of the main gate signal, and the enable time of the main gate signal is earlier than an enable time of the second gate reference signal.

4. The shift register according to claim 1, wherein the voltage setting unit comprises:

a fifth transistor having a first end configured to receive the first gate reference signal, a second end configured to provide the terminal voltage, and a control end configured to receive the first gate reference signal.

5. The shift register according to claim 1, wherein the drive unit comprises:

a sixth transistor having a first end configured to receive the clock signal, a second end configured to provide the main gate signal, and a control end configured to receive the terminal voltage; and

a first capacitor, coupled between the control end of the sixth transistor and the second end of the sixth transistor.

6. The shift register according to claim 1, wherein the first control unit comprises:

a seventh transistor having a first end configured to receive the first latch reference signal, a second end, and a control end coupled to the first end of the seventh transistor;

an eighth transistor having a first end coupled to the second end of the seventh transistor, a second end configured to receive the first low voltage, and a control end configured to receive the terminal voltage;

a ninth transistor having a first end configured to receive the first latch reference signal, a second end configured to provide the first control signal, and a control end coupled to the second end of the seventh transistor; and

a tenth transistor having a first end coupled to the second end of the ninth transistor, a second end configured to receive the first low voltage, and a control end configured to receive the terminal voltage.

7. The shift register according to claim 1, wherein the drive unit receives the terminal voltage and the clock signal so as to provide the main gate signal and a secondary gate signal according to the terminal voltage and the clock signal.

8. The shift register according to claim 7, wherein the drive unit comprises:

an eleventh transistor having a first end configured to receive the clock signal, a second end configured to provide the secondary gate signal, and a control end configured to receive the terminal voltage;

a twelfth transistor having a first end configured to receive the clock signal, a second end configured to provide the main gate signal, and a control end configured to receive the terminal voltage; and

a second capacitor coupled between the control end of the twelfth transistor and the second end of the twelfth transistor.

9. The shift register according to claim 7, wherein the voltage setting unit receives the first gate reference signal, a third gate reference signal and the main gate signal so as to provide the terminal voltage, wherein enable times of the first gate reference signal and the third gate reference signal completely overlap.

10. The shift register according to claim 9, wherein the voltage setting unit comprises:

a thirteenth transistor having a first end configured to receive the first gate reference signal, a second end, and a control end configured to receive the third gate reference signal;

a fourteenth transistor having a first end coupled to the second end of the thirteenth transistor, a second end configured to provide the terminal voltage, and a control end configured to receive the third gate reference signal; and

a fifteenth transistor having a first end coupled to the second end of the thirteenth transistor, a second end configured to receive the main gate signal, and a control end configured to receive the main gate signal.

11. The shift register according to claim 7, wherein the level reference signal is the secondary gate signal, the first low voltage is higher than the second low voltage, and the first latch reference signal is a gate high voltage.

12. The shift register according to claim 11, further comprising:

a sixteenth transistor having a first end configured to receive the main gate signal, a second end configured to receive a third low voltage, and a control end configured to receive a first control voltage, wherein the second low voltage is higher than the third low voltage.

13. The shift register according to claim 12, further comprising:

a seventeenth transistor having a first end configured to receive the terminal voltage, a second end configured to receive the first low voltage, and a control end configured to receive the second gate reference signal.

14. The shift register according to claim 12, further comprising:

a second control unit configured to receive a second latch reference signal, the terminal voltage and the first low voltage, so as to provide a second control signal, wherein the second latch reference signal and the first latch reference signal are inverted with respect to each other;

an eighteenth transistor having a first end configured to receive the terminal voltage, a second end configured to receive the secondary gate signal, and a control end configured to receive the second control signal;

a nineteenth transistor having a first end coupled to the second end of the eighteenth transistor, a second end configured to receive the second low voltage, and a control end configured to receive the second control signal; and

a twentieth transistor having a first end configured to receive the main gate signal, a second end configured to receive the third low voltage, and a control end configured to receive the second control signal.

15. The shift register according to claim 14, wherein the second control unit comprises:

a twenty-first transistor having a first end configured to receive the second latch reference signal, a second end, and a control end coupled to the first end of the twenty-first transistor;

a twenty-second transistor having a first end coupled to the second end of the twenty-first transistor, a second end configured to receive the first low voltage, and a control end configured to receive the terminal voltage;

a twenty-third transistor having a first end configured to receive the second latch reference signal, a second end configured to provide the second control signal, and a control end coupled to the second end of the twenty-first transistor; and

a twenty-fourth transistor having a first end coupled to the second end of the twenty-third transistor, a second end configured to receive the first low voltage, and a control end configured to receive the terminal voltage.

16. A liquid crystal display (LCD) panel, comprising:

a glass substrate; and

a shift register disposed on the glass substrate, the shift register comprising;

a voltage setting unit configured to receive a first gate reference signal so as to provide a terminal voltage;

a drive unit configured to receive the terminal voltage and a clock signal, so as to provide a main gate signal according to the terminal voltage and the clock signal;

a first control unit configured to receive a first latch reference signal, the terminal voltage and a first low voltage, so as to provide a first control signal;

a first transistor having a first end configured to receive the terminal voltage, a second end configured to receive a level reference signal, and a control end configured to receive the first control signal;

a second transistor having a first end coupled to the second end of the first transistor, a second end configured to receive a second low voltage, and a control end configured to receive the first control signal;

a third transistor having a first end configured to receive the terminal voltage, a second end configured to receive the level reference signal, and a control end configured to receive a second gate reference signal; and

a fourth transistor having a first end coupled to the second end of the third transistor, a second end configured to receive the second low voltage, and a control end configured to receive the second gate reference signal.

17. The LCD panel according to claim 16, wherein the voltage setting unit comprises:

a fifth transistor having a first end configured to receive the first gate reference signal, a second end configured to provide the terminal voltage, and a control end configured to receive the first gate reference signal.

18. The LCD panel according to claim 16, wherein the drive unit comprises:

a sixth transistor having a first end configured to receive the clock signal, a second end configured to provide the main gate signal, and a control end configured to receive the terminal voltage; and

a first capacitor, coupled between the control end of the sixth transistor and the second end of the sixth transistor.

19. The LCD panel according to claim 16, wherein the first control unit comprises:

a seventh transistor having a first end configured to receive the first latch reference signal, a second end, and a control end coupled to the first end of the seventh transistor;

an eighth transistor having a first end coupled to the second end of the seventh transistor, a second end configured to receive the first low voltage, and a control end configured to receive the terminal voltage;

a ninth transistor having a first end configured to receive the first latch reference signal, a second end configured to provide the first control signal, and a control end coupled to the second end of the seventh transistor; and

a tenth transistor having a first end coupled to the second end of the ninth transistor, a second end configured to receive the first low voltage, and a control end configured to receive the terminal voltage.