SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF

• US 20170125305A1
• Filed: 10/24/2016
• Published: 05/04/2017
• Est. Priority Date: 11/04/2015
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: ZHOU, FEI
• Granted Patent: US 10,685,889 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/42364 : characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4966 : the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 : the body having a non-rectangular crossection

Abstract

A method for fabricating a semiconductor structure includes providing a substrate including a core region and a peripheral region, forming a plurality of first fin structures in the peripheral region and a plurality of second fin structures in the core region, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure, and forming a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure and then forming a first gate oxide layer on the exposed portion of each first fin structure, and removing each second dummy gate structure. Finally, the method includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.

Claims

1. A method for fabricating a semiconductor structure, comprising:

forming a semiconductor base structure including a substrate and a plurality of fin structures formed on the substrate, wherein the substrate includes a peripheral region and a core region, fin structures formed in the peripheral region are first fin structures, and fin structures formed in the core region are second fin structures;

forming a first dummy gate structure on each first fin structure and a second dummy gate structure on each second fin structure;

forming a dielectric layer on the semiconductor base structure, wherein a top surface of the dielectric layer is leveled with top surfaces of the first dummy gate structures and the second dummy gate structures;

removing each first dummy gate structure to form a first opening in the dielectric layer, wherein a portion of the first fin structure is exposed in the first opening;

forming a first gate oxide layer on the exposed portion of each first fin structure;

removing each second dummy gate structure to form a second opening in the dielectric layer, wherein a portion of the second fin structure is exposed in the second opening;

forming a gate dielectric layer to cover each first gate oxide layer, sidewall surfaces of each first opening, and bottom and sidewall surfaces of each second opening; and

forming a metal layer to cover the gate dielectric layer and fill up the first openings and the second openings, wherein the first gate oxide layer, the gate dielectric layer, and the metal layer formed in each first opening form a first gate structure, and the gate dielectric layer and the metal layer formed in each second opening form a second gate structure.

2. The method for fabricating the semiconductor structure according to claim 1, wherein the first gate oxide layer is made of SiO_x.

3. The method for fabricating the semiconductor structure according to claim 1, wherein the first gate oxide layer is formed by an in-situ steam generation (ISSG) oxidation process, and process parameters used in the ISSG oxidation process include:

a process gas including O₂ and H₂;

a flow rate of O₂ in a range of 1 sccm to 30 sccm;

a flow rate of H₂ in a range of 1.5 sccm to 15 sccm; and

a chamber temperature in a range of 700°

C. to 1200°

C.

4. The method for fabricating the semiconductor structure according to claim 1, wherein the dielectric layer is made of one of HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO₂, and Al₂O₃.

5. The method for fabricating the semiconductor structure according to claim 1, wherein the core region and the peripheral region are both P-type regions, or both N-type regions.

6. The method for fabricating the semiconductor structure according to claim 5, wherein:

after forming the gate dielectric layer but prior to filling the first openings and the second openings with the metal layer, a work function layer is formed on the gate dielectric layer;

when the core region and the peripheral region are both N-type regions, the work function layer is made of an N-type work function material; and

when the core region and the peripheral region are both P-type regions, the work function layer is made of a P-type work function material.

7. The method for fabricating the semiconductor structure according to claim 6, wherein:

when the core region and the peripheral region are both N-type regions, the N-type work function layer is made of one or more of TiAl, TaAlN, TiAlN, MoN, TaCN, and AlN; and

when the core region and the peripheral region are both P-type regions, the P-type work function layer is made of one or more of Ta, TiN, TaN, TaSiN, and TiSiN.

8. The method for fabricating the semiconductor structure according to claim 1, wherein the metal layer is made of one of Al, Cu, Ag, Au, Pt, Ni, Ti, and W.

9. The method for fabricating the semiconductor structure according to claim 1, wherein:

the first dummy gate structure includes a first dummy gate oxide layer and a first dummy gate electrode layer formed on the first dummy gate oxide layer;

the second dummy gate structure includes a second dummy gate oxide layer and a second dummy gate electrode layer formed on the second dummy gate oxide layer; and

the first dummy gate structure and the second dummy gate structure are formed by a process including;

forming a dummy gate oxide film to cover the first fin structures and the second fin structures;

forming a dummy gate electrode film on the dummy gate oxide film;

forming a first patterned layer on the dummy gate electrode film, wherein positions, shapes, and dimensions of the first patterned layer define positions, shapes, and dimensions for subsequently-formed dummy gate electrode layers;

performing an etching process to etch the dummy gate electrode film and the dummy gate oxide film to form a first dummy gate structure on each first fin structure in the peripheral region and form a second dummy gate structure on each second fin structure in the core region, wherein the first dummy gate structure includes a first dummy gate oxide layer and a first dummy gate electrode layer, and the second dummy gate structure includes a second dummy gate oxide layer and a second dummy gate electrode layer; and

removing the first patterned layer.

10. The method for fabricating the semiconductor structure according to claim 1, wherein each first dummy gate structure includes a first dummy gate oxide layer and a first dummy gate electrode layer formed on the first dummy gate oxide layer, and removing the first dummy gate structure includes:

forming a second patterned layer to cover the core region, wherein the second patterned layer exposes a top surface of the first dummy gate electrode layer;

performing a dry etching process to remove the first dummy gate electrode layer and the first dummy gate oxide layer using the second patterned layer as an etch mask until a portion of the first fin structure is exposed and a first opening is formed in the dielectric layer; and

removing the second patterned layer.

11. The method for fabricating the semiconductor structure according to claim 1, wherein the second dummy gate structure includes a second dummy gate oxide layer and a second dummy gate electrode layer formed on the second dummy gate oxide layer, and removing the second dummy gate structure includes:

forming a third patterned layer to cover the peripheral region, wherein the third patterned layer exposes a top surface of the second dummy gate electrode layer;

performing a dry etching process to remove the second dummy gate electrode layer and then the second dummy gate oxide layer using the third patterned layer as an etch mask until a portion of the second fin structure is exposed and a second opening is formed in the dielectric layer; and

removing the third patterned layer.

12. The method for fabricating a semiconductor structure according to claim 6, wherein the first gate structure and the second gate structure are formed by a process including:

forming the gate dielectric layer on the first gate oxide layer in each first opening, sidewall surfaces of each first opening, and bottom and sidewall surfaces of each second opening, wherein the gate dielectric layer also covers the top surface of the dielectric layer;

forming a work function layer on the gate dielectric layer;

forming a metal layer on the work function layer to fill up the first openings and the second openings, wherein a top surface of the metal layer is higher than the top surface of the dielectric layer;

removing a portion of the metal layer formed above the dielectric layer to form a first gate electrode layer on the work function layer in each first opening in the peripheral region and a second gate electrode layer on the work function layer in each second opening in the core region; and

removing a portion of the gate dielectric layer and the work function layer formed above the dielectric layer to form a first gate dielectric layer on each first gate oxide layer as well as sidewall surfaces of the corresponding first opening in the peripheral region, a first work function layer on each first gate dielectric layer, a second gate dielectric layer on bottom and sidewall surfaces of each second opening in the core region, and a second work function layer on each second gate dielectric layer, wherein,

the first gate oxide layer, the first gate dielectric layer, the first work function layer, and the first gate electrode layer in each first opening together form a first gate structure; and

the second gate dielectric layer, the second work function layer, and the second gate electrode layer together form a second gate structure.

13. The method for fabricating the semiconductor structure according to claim 12, wherein:

after removing the second dummy gate structures and prior to forming the gate dielectric layer, an interface layer is formed on the first gate oxide layer in each first opening, sidewall surfaces of each first opening, and bottom and sidewall surfaces of each second opening, wherein the interface layer also covers the top surface of the dielectric layer; and

in the course of removing the portion of the metal layer, the work function layer, and the gate dielectric layer formed above the dielectric layer, a portion of the interface layer formed above the dielectric layer is also removed to form a first interface layer on each first gate oxide layer as well as sidewall surfaces of the corresponding first opening in the peripheral region, and a second interface layer on bottom and sidewall surfaces of each second opening in the core region.

14. The method for fabricating the semiconductor structure according to claim 1, wherein:

the first dummy gate structure includes a first dummy gate oxide layer and a first dummy gate electrode layer formed on the first dummy gate oxide layer;

the second dummy gate structure includes a second dummy gate oxide layer and a second dummy gate electrode layer formed on the second dummy gate oxide layer;

the first dummy gate electrode layer is made of one of polycrystalline silicon, SiO_x, SiN_x, SiON, SiCN, SiCON, and amorphous silicon; and

the second dummy gate electrode layer is made of one of polycrystalline silicon, SiO_x, SiN_x, SiON, SiCN, SiCON, and amorphous silicon.

15. The method for fabricating the semiconductor structure according to claim 1, wherein after forming the first dummy gate structure on each first fin structure and the second dummy structure on each second fin structure and prior to forming the dielectric layer on the semiconductor base structure, further including:

forming a first peripheral-region sidewall spacer on each sidewall surface of the first dummy fin structure and a first core-region sidewall spacer on each sidewall surface of the second dummy fin structure;

forming a peripheral-region stress layer in the first fin structure on each side of the first dummy gate structure and a core-region stress layer in the second fin structure on each side of the second dummy gate structure;

forming a second peripheral-region sidewall spacer on a sidewall surface of each first peripheral-region sidewall spacer and a second core-region sidewall spacer on a sidewall surface of each first core-region sidewall spacer; and

forming a peripheral-region source region and a peripheral-region drain region in the first fin structure and the peripheral-region stress layer on each side of the first dummy gate structure and a core-region source region and a core-region drain region in the second fin structure and the core-region stress layer on each side of the second dummy gate structure.

16. The method for fabricating the semiconductor structure according to claim 15, wherein:

the peripheral-region stress layer is made of silicon;

the peripheral-region stress layer is formed by an epitaxial chemical vapor deposition growth process;

the core-region stress layer is made of silicon; and

the core-region stress layer is formed by an epitaxial chemical vapor deposition growth process.

17. The method for fabricating the semiconductor structure according to claim 16, wherein process parameters used in the epitaxial chemical vapor deposition growth process include:

a process temperature in a range of 500°

C. to 950°

C.;

a process time in a range of 1000 s to 11000 s;

a chamber pressure in a range of 5 Torr to 1000 Torr;

a pretreatment gas of H₂; and

a reaction gas including one or more of HCl, SiH₂Cl₂, and SiH₄.

18. A semiconductor structure, comprising:

a semiconductor base structure including a substrate and a plurality of fin structures formed on the substrate, wherein the substrate includes a peripheral region and a core region, fin structures formed in the peripheral region are first fin structures, and fin structures formed in the core region are second fin structures;

a first gate structure formed on a portion of each first fin structure in the peripheral region and a second gate structure formed on a portion of each second fin structure in the core region; and

a dielectric layer formed on the semiconductor base structure, wherein a top surface of the dielectric layer is leveled with top surfaces of the first gate structures and the second gate structures, wherein;

each first gate structure is formed on the portion of the first fin structure in the peripheral region after removing a first dummy gate structure initially formed on the first fin structure to form a first opening in the dielectric layer and expose the portion of the first fin structure;

each second gate structure is formed on the portion of the second fin structure in the core region after removing a second dummy gate structure initially formed on the second fin structure to form a second opening in the dielectric layer and expose the portion of the second fin structure;

each first gate structure in the peripheral region includes a first gate oxide layer formed on the first fin structure, a gate dielectric layer formed on the first gate oxide layer and sidewall surfaces of the corresponding first opening, and a first gate electrode layer formed on the first gate dielectric layer; and

each second gate structure in the core region includes a second gate dielectric layer formed on the second fin structure and sidewall surfaces of the corresponding second opening, and a second gate electrode layer formed on the second gate dielectric layer.

19. The semiconductor structure according to claim 18, wherein:

the first gate structure also includes a first interface layer formed on the first gate oxide layer and sidewall surfaces of the corresponding first opening;

the first gate dielectric layer is formed on the first interface layer;

the second gate structure also includes a second interface layer formed on the exposed portion of the second fin structure in the second opening and also on sidewall surfaces of the corresponding second opening; and

the second gate dielectric layer is formed on the second interface layer.

20. The semiconductor structure according to claim 18, wherein:

the first gate structure also includes a first work function layer formed between the first gate dielectric layer and the first gate electrode layer; and

the second gate structure also includes a second work function layer formed between the second gate dielectric layer and the second gate electrode layer.