METHOD TO CONTROL THE COMMON DRAIN OF A PAIR OF CONTROL GATES AND TO IMPROVE INTER-LAYER DIELECTRIC (ILD) FILLING BETWEEN THE CONTROL GATES

• US 20170125434A1
• Filed: 01/18/2017
• Published: 05/04/2017
• Est. Priority Date: 08/26/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Min, Chung-Chiang, Yang, Tsung-Hsueh, Wu, Chang-Ming, Liu, Shih-Chang
• Granted Patent: US 10,276,584 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

Claims

1. A method for manufacturing a split gate flash memory cell, the method comprising:

forming a stack over a semiconductor substrate, wherein the stack includes a control gate layer and a sacrificial layer over the control gate layer;

forming a charge trapping dielectric layer and a memory gate layer lining sidewalls of the stack, wherein the memory gate layer is formed over the charge trapping dielectric layer;

removing the sacrificial layer to form a recess between sidewalls of the charge trapping dielectric layer;

forming a pair of hard masks in the recess, wherein the hard masks are formed laterally spaced and respectively on opposite sides of the recess;

removing a central portion of the control gate layer between the hard masks to form a pair of control gates masked by the hard masks; and

removing lateral portions of the memory gate layer, while removing the central portion of the control gate layer, to form a pair of memory gates corresponding to the control gates.

2. The method according to claim 1, wherein the hard masks are formed with asymmetric profiles decreasing in height towards the central portion of the control gate layer.

3. The method according to claim 1, wherein forming the pair of hard masks comprises:

forming a hard mask layer conformally lining the recess; and

performing an etch into the hard mask layer to remove a lateral portion of the hard mask layer and to form the pair of hard masks.

4. The method according claim 1, further including:

before removing the sacrificial layer, performing a planarization into the charge trapping dielectric layer and the memory gate layer to a top surface of the sacrificial layer.

5. The method according to claim 4, further including:

forming a second sacrificial layer over and around the memory gate layer before performing the planarization, wherein the planarization is further performed into the second sacrificial layer; and

removing the second sacrificial layer after forming the hard masks.

6. The method according to claim 1, further including:

forming an inter-layer dielectric (ILD) layer over and around the memory gates and the control gates, and continuously filling a region between the control gates; and

performing a planarization or etch back through the hard masks and into the ILD layer to top surfaces of the control gates.

7. The method according to claim 6, further including:

forming a second ILD layer over the top surfaces of the control gates and the remaining ILD layer; and

forming contacts extending through the remaining ILD layer and the second ILD layer to source/drain regions in the semiconductor substrate.

8. The method according to claim 6, further including:

forming a main sidewall structure along sidewalls of the memory gates and sidewalls of the control gates; and

forming a contact etch stop layer conformally over the main sidewall structure, the charge trapping dielectric layer, the memory gates, and the hard masks; and

wherein the ILD layer is formed over the main sidewall structure and the contact etch stop layer.

9. A method for manufacturing a split gate flash memory cell, the method comprising:

forming a multilayer stack over a semiconductor substrate, wherein the multilayer stack includes a first gate layer and a sacrificial layer covering the first gate layer;

forming a second gate layer covering the semiconductor substrate and the multilayer stack, and further lining sidewalls of the multilayer stack;

performing a planarization into the second gate layer to coplanarize a top surface of the second gate layer with a top surface of the sacrificial layer;

performing a first etch into the sacrificial layer to remove the sacrificial layer and to form a recess in place of the sacrificial layer;

forming a pair of hard masks in the recess, wherein the hard masks are formed laterally spaced and respectively on opposite sides of the recess; and

performing a second etch into the first and second gate layers to form first gate electrodes covered by the hard masks and second gate electrodes bordering the first gate electrodes.

10. The method according to claim 9, wherein forming the multilayer stack comprises:

forming the first gate layer over the semiconductor substrate;

forming the sacrificial layer covering the first gate layer; and

performing a third etch into the first gate layer and the sacrificial layer to form the multilayer stack from the first gate layer and the sacrificial layer.

11. The method according to claim 9, further comprising:

forming a second sacrificial layer covering the second gate layer and the multilayer stack, and further lining sidewalls of the second gate layer, wherein the planarization is performed into the second sacrificial layer to coplanarize a top surface of the second sacrificial layer with the top surfaces respectively of the sacrificial layer and the second gate layer; and

performing a third etch into the second sacrificial layer to remove the second sacrificial layer, wherein the third etch is performed after forming the pair of hard masks.

12. The method according to claim 9, wherein forming the pair of hard masks comprises:

forming a hard mask layer covering the second gate layer and conformally lining the recess, such that that the hard mask layer comprises a U-shaped profile in the recess; and

performing a third etch into the hard mask layer to remove lateral portions of the hard mask layer and to form the pair of hard masks.

13. The method according to claim 9, wherein the hard masks are each formed with a top surface slanting downward towards a gap between the hard masks.

14. The method according to claim 9, further comprising:

forming a charge trapping dielectric layer covering and contacting the semiconductor substrate and the multilayer stack, and further lining and contacting the sidewalls of the multilayer stack, wherein the planarization is performed into the charge trapping dielectric layer to coplanarize a top surface of the charge trapping dielectric layer with the top surfaces respectively of the second gate layer and the sacrificial layer, and wherein the second etch is performed into the charge trapping dielectric layer.

15. The method according to claim 14, wherein the pair of hard masks are formed such that the hard masks contact sidewalls of the charge trapping dielectric layer.

16. The method according to claim 9, further comprising:

forming a dielectric layer covering the semiconductor substrate, the first and second gate electrodes, and the hard masks, and further lining and contacting sidewalls of the first and second gate electrodes and sidewalls of the hard masks; and

performing a third etch into the dielectric layer to remove lateral portions of the dielectric layer and to form a main sidewall structure from the dielectric layer, wherein the main sidewall structure is formed lining and contacting the sidewalls of the first and second gate electrodes and the sidewalls of the hard masks.

17. The method according to claim 16, further comprising:

implanting dopants into the semiconductor substrate with the main sidewall structure in place to form a source/drain region between the first gate electrodes;

forming an interlayer dielectric (ILD) layer covering the semiconductor substrate, the first and second gate electrodes, the hard masks, and the source/drain region; and

forming a contact via extending through the ILD layer to the source/drain region from a top surface of the ILD layer.

18. A method for manufacturing a split gate flash memory cell, the method comprising:

forming a multilayer stack over a semiconductor substrate and comprising a first gate layer and a first sacrificial layer, wherein the first sacrificial layer covers the first gate layer and has opposite sidewalls respectively aligned with opposite sidewalls of first gate layer;

forming a second gate layer covering the multilayer stack and the semiconductor substrate, and further lining sidewalls of the multilayer stack;

forming a second sacrificial layer covering the second gate layer and lining sidewalls of the second gate layer;

performing a planarization into the second sacrificial layer and the second gate layer to expose a top surface of the first sacrificial layer;

performing a first etch into the first sacrificial layer to remove the first sacrificial layer, and to define an opening in place of the first sacrificial layer;

forming a hard mask layer covering the second sacrificial layer and the second gate layer, and further lining the opening;

performing a second etch into the hard mask layer to remove lateral portions of the hard mask layer and to form a pair of hard masks, wherein the hard masks are formed in the opening and respectively on opposite sides of the opening;

performing a third etch into the second sacrificial layer to remove the second sacrificial layer; and

performing a fourth etch into the first and second gate layers with the hard masks in place to simultaneously form a pair of first gate electrodes and a pair of second gate electrodes, wherein the first gate electrodes are formed respectively covered by the hard masks, and the second gate electrodes are formed respectively bordering the first gate electrodes.

19. The method according to claim 18, further comprising:

forming a charge trapping dielectric layer covering and contacting the semiconductor substrate and the multilayer stack, and further lining and contacting sidewalls of the first gate layer and the first sacrificial layer;

wherein the planarization is performed into the charge trapping dielectric layer to coplanarize a top surface of the charge trapping dielectric layer with the top surface of the first sacrificial layer, and wherein the fourth etch is performed into the charge trapping dielectric layer to remove lateral portions of the charge trapping layer that are uncovered.

20. The method according to claim 18, further comprising:

forming an interlayer dielectric (ILD) layer covering the semiconductor substrate, the first and second gate electrodes, and the hard masks; and

forming a contact via extending through the ILD layer to the semiconductor substrate from a top surface of the ILD layer.