CONTROLLERS FOR WIRELESS POWER SYSTEMS

• US 20170126069A1
• Filed: 10/31/2016
• Published: 05/04/2017
• Est. Priority Date: 10/29/2015
• Status: Active Grant

• Current Assignee: WiTricity Corporation
• Original Assignee: WiTricity Corporation
• Inventors: Martin, Bradley
• Granted Patent: US 9,762,093 B2
• Time in Patent Office: Days
• CPC Class Codes: H02J 50/12 of the resonant type
• CPC Class Codes: H02M 3/04 by static converters
• CPC Class Codes: H02M 7/04 by static converters
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

The disclosure features high-resolution pulse-width modulation (HRPWM) controllers that can include a first channel having a first coarse_on register and a first coarse_off register and a counter configured to determine a repetition rate for the first channel. When a coarse_on value of the first coarse_on register and the counter are equal, the first channel can be set “active” and when a coarse_off value of the first coarse_off register and the counter are equal, the first channel can be set “inactive”. The controllers can include a delay line configured to generate a set of delay locked waveforms offset by a fine resolution value and a control module configured to select a delay locked waveform from the set of delay locked waveforms and apply the selected delay locked waveform to the first channel.

Claims

1. A high-resolution pulse-width modulation (HRPWM) controller comprising:

a first channel having a first coarse_on register and a first coarse_off register;

a counter configured to determine a repetition rate for the first channel, wherein;

when a coarse_on value of the first coarse_on register and the counter are equal, the first channel is set “

active”

;

when a coarse_off value of the first coarse_off register and the counter are equal, the first channel is set “

inactive”

; and

a delay line configured to generate a set of delay locked waveforms offset by a fine resolution value;

a control module configured to select a delay locked waveform from the set of delay locked waveforms and apply the selected delay locked waveform to the first channel.

2. The HRPWM controller of claim 1 further comprising a second channel having a second coarse_on register and a second coarse_off register to determine a second coarse resolution value associated with the second channel.

3. The HRPWM controller of claim 2 wherein the first and second channels of the HRPWM controller are configured to control a first switching element and a second switching element of a class E full-bridge inverter, class D half-bridge inverter, or a half-bridge converter.

4. The HRPWM controller of claim 2 further comprising two additional channels.

5. The HRPWM controller of claim 4 wherein each of the four channels of the HRPWM controller are configured to control a corresponding switching element of a class D full-bridge inverter.

6. The HRPWM controller of claim 4 wherein each of the four output channels of the HRPWM controller are configured to control a corresponding switching element of a converter.

7. The HRPWM controller of claim 1 wherein the delay line is a phase-locked loop (PLL) or delay-locked loop (DLL).

8. The HRPWM controller of claim 1 wherein the fine resolution value determines which of the set of delayed intervals is applied to a multiplexer that selects from the set of delay locked waveforms.

9. The HRPWM controller of claim 1 wherein the first coarse_on register and the first coarse_off register determine a first coarse resolution value associated with the first channel and wherein increasing the fine resolution value on the coarse resolution value delays start of first channel and reduces a pulse width of the first channel.

10. The HRPWM controller of claim 1 wherein setting equal the fine resolution value on the coarse_on value to the fine resolution value on the coarse_off value maintains a pulse width of the first channel.

11. The HRPWM controller of claim 10 wherein setting equal the fine resolution value shifts first channel from its original position.

12. A method to generate a first HRPWM signal, the method comprising:

providing a first channel having a first coarse_on register and a first coarse_off register;

comparing a coarse_on value of the first coarse_on register to a counter, the counter configured to determine a repetition rate for the first channel, wherein when the coarse_on value of the first coarse_on register and the counter are equal, the first channel is set “

active”

;

comparing a coarse_off value of the first coarse_off register to the counter, wherein when the coarse_off value of the first coarse_off register and the counter are equal, the first channel is set “

inactive”

;

generating a set of delay locked waveforms offset by a fine resolution value; and

applying a selected delay locked waveform from the set of delay locked waveforms to the first channel.

13. The method of claim 12 further comprising generating an N^th HRPWM signal by:

providing a N^th channel having a N^th coarse_on register and a N^th coarse_off register;

comparing a coarse_on value of the N^th coarse_on register to the counter, the counter configured to determine a repetition rate for the N^th channel, wherein when the coarse_on value of the N^th coarse_on register and the counter are equal, the N^th channel is set “

active”

;

comparing a coarse_off value of the N^th coarse_off register to the counter, wherein when the coarse_off value of the N^th coarse_off register and the counter are equal, the N^th channel is set “

inactive”

;

generating, via a delay line, a set of delay locked waveforms offset by a fine resolution value; and

applying a selected delay locked waveform from the set of delay locked waveforms to the N^th channel.

14. The method of claim 13 wherein N=2 and each of the two channels are configured to control a corresponding switching element of a converter or inverter.

15. The method of claim 13 wherein N=4 and each of the four channels are configured to control a corresponding switching element of a converter or inverter.

16. The method of claim 12 wherein the delay line is a phase-locked loop (PLL) or delay-locked loop (DLL).

17. The method of claim 12 wherein the fine resolution value determines which of the set of delayed intervals is applied to a multiplexer that outputs the selected delay locked waveform.

18. The method of claim 12 wherein the first coarse_on register and first coarse_off register determine a first coarse resolution value and wherein increasing the fine resolution value on the coarse resolution value delays start of first channel and reduces a pulse width of the first channel.

19. The method of claim 12 wherein setting equal the fine resolution value on the coarse_on value to the fine resolution value on the coarse_off value maintains a pulse width of the first channel.

20. The method of claim 19 wherein setting equal the fine resolution value shifts first channel from its original position.