SIMULATION OF MODIFICATIONS TO MICROPROCESSOR DESIGN

• US 20170132341A1
• Filed: 04/22/2016
• Published: 05/11/2017
• Est. Priority Date: 11/11/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Berry, Christopher J., Neves, Jose L., Wood, Michael H., Cavitt, Chris A., Matheny, Adam P., Surprise, Jesse P.
• Granted Patent: US 9,928,322 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

Claims

1. A computer-implemented method comprising:

identifying a first open path in a microprocessor design;

simulating at least one modification to a design of the first open path;

calculating an updated arrival time at a first pin based on the at least one simulated modification; and

calculating a first updated path time based on the updated arrival time.

2. The method of claim 1 wherein simulating at least one modification comprises estimating an effect of the at least one modification without designing the at least one modification.

3. The method of claim 1, further comprising using the first updated path time to determine a criticality of the first open path by:

identifying a required time for the first open path; and

subtracting the required time from the first updated path time.

4. The method of claim 3, further comprising comparing the criticality of the first open path with the criticality of a second open path in the microprocessor design.

5. The method of claim 3, further comprising designing an integration solution that incorporates the at least one simulated modification of the first open path that exhibits a criticality of zero or greater.

6. The method of claim 1, wherein simulating at least one modification comprises:

identifying a net on the first open path;

identifying a beginning point of the net and an ending point of the net;

identifying an integration distance of the net;

identifying a modified Manhattan Distance between the beginning point and ending point; and

substituting the modified Manhattan Distance for the integration distance.

7. The method of claim 6, wherein the modified Manhattan Distance is a minimum Manhattan Distance.

8. The method of claim 6, further comprising simulating a stipulated integration speed over the modified Manhattan Distance.

9. The method of claim 8, wherein the stipulated integration speed is determined based on the wire speed and speed of one or more repeaters on the net.

10. The method of claim 1, wherein simulating at least one modification comprises:

identifying a net on the first open path;

identifying a first layer on which the net is located;

identifying an integration speed of a second layer on the first open path, wherein the integration speed of the second layer is different from an integration speed of the first layer; and

substituting the integration speed of the second layer for the integration speed of the first layer over the net.

11. The method of claim 10, wherein the substituting the integration speed of the second layer for the integration speed of the net comprises:

locating a hierarchal pin that connects the first layer to the second layer; and

relocating the hierarchal pin to a beginning of the net.

12. The method of claim 1, wherein simulating at least one modification comprises:

identifying a pin on the path based on the potential of a long rise/fall time at the pin; and

applying a shorter rise/fall time at the pin.

13. The method of claim 12, wherein applying a shorter rise/fall time comprises applying a rate of voltage change per time at the pin.

14. The method of claim 12, wherein applying a shorter rise/fall time comprises:

establishing a maximum amount of time for a voltage change at the pin; and

reducing the amount of time for the voltage change at the pin to the maximum amount of time.

15. The method of claim 1, wherein the first pin comprises a pin that is nearest to and downstream of the at least one simulated modification.

16. The method of claim 1, wherein simulating the at least one modification comprises:

simulating an integration distance reduction to the open path, comprising;

identifying a first net on the open path;

identifying a beginning point of the net and an ending point of the net;

identifying an integration distance for the net;

identifying a modified Manhattan Distance between the beginning point and ending point; and

substituting the modified Manhattan Distance for the integration distance;

simulating an integration-speed substitution to a second net on the path, comprising;

identifying the second net on the open path;

identifying a first layer on which the second net is located;

identifying an integration speed of a second layer, wherein the integration speed of the second layer is different from an integration speed of the first layer; and

substituting the integration speed of the second layer for the integration speed of the first layer over the net;

simulating a decrease to a rise/fall time on a pin, comprising;

identifying a pin on the path based on the potential of a long rise/fall time at the pin; and

applying a shorter rise/fall time at the pin.