HIGH CAPACITY MEMORY SYSTEMS
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Abstract
In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
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Citations
40 Claims
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1-20. -20. (canceled)
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21. A method of operation within a memory control component, the method comprising:
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outputting a sequence of command/address values via a command/address bus coupled in common to respective command/address inputs of first and second memory components; asserting, at respective times, a first chip-select signal that enables the first memory component to sample a first command/address value in the sequence of command/address values and a second chip-select signal that enables the second memory component to sample a second command/address value in the sequence of command address values; outputting first and second timing signals to the first and second memory components, respectively, the first timing signal to control a first sampling instant at which the first memory component samples the first command/address value and the second timing signal to control a second sampling instant at which the second memory component samples the second command/address value; and establishing a timing offset between the first and second timing signals that compensates at least for a difference between respective first and second timing signal propagation delays within the first and second memory components, the first timing signal propagation delay corresponding to a time interval between arrival of the first timing signal at the first memory component and the first sampling instant, and the second timing signal propagation delay corresponding to a time interval between arrival of the second timing signal at the second memory component and the second sampling instant. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A memory control component comprising:
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a command/address interface to output a sequence of command/address values via a command/address bus coupled in common to respective command/address inputs of first and second memory components; a chip-select interface to assert, at respective times, a first chip-select signal that enables the first memory component to sample a first command/address value in the sequence of command/address values and a second chip-select signal that enables the second memory component to sample a second command/address value in the sequence of command address values; and timing circuitry to; output first and second timing signals to the first and second memory components, respectively, the first timing signal to control a first sampling instant at which the first memory component samples the first command/address value and the second timing signal to control a second sampling instant at which the second memory component samples the second command/address value; establish a timing offset between the first and second timing signals that compensates at least for a difference between respective first and second timing signal propagation delays within the first and second memory components, the first timing signal delay corresponding to a time interval between arrival of the first timing signal at the first memory component and the first sampling instant, and the second timing signal delay corresponding to a time interval between arrival of the second timing signal at the second memory component and the second sampling instant. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38)
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39. An integrated circuit (IC) package comprising:
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first and second memory ICs; a command/address bus coupled in common to the first and second memory ICs; first and second chip-select links coupled respectively to the first and second memory ICs; first and second timing signal links coupled respectively to the first and second memory ICs; and a memory control IC having; a command/address interface to output a sequence of command/address values via the command/address bus; a chip-select interface to assert at respective times (i) a first chip-select signal via the first chip-select link to enable the first memory component to sample a first command/address value in the sequence of command/address values, and (ii) a second chip-select signal via the second chip-select link to enable the second memory component to sample a second command/address value in the sequence of command address values; and timing circuitry to; output first and second timing signals to the first and second memory components via the first and second timing signal links, respectively, the first timing signal to control a first sampling instant at which the first memory component samples the first command/address value and the second timing signal to control a second sampling instant at which the second memory component samples the second command/address value; establish a timing offset between the first and second timing signals that compensates at least for a difference between respective first and second timing signal propagation delays within the first and second memory components, the first timing signal delay corresponding to a time interval between arrival of the first timing signal at the first memory component and the first sampling instant, and the second timing signal delay corresponding to a time interval between arrival of the second timing signal at the second memory component and the second sampling instant. - View Dependent Claims (40)
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Specification