HIGH CAPACITY MEMORY SYSTEMS

• US 20170133070A1
• Filed: 12/26/2016
• Published: 05/11/2017
• Est. Priority Date: 03/19/2012
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Leibowitz, Brian S., Ellis, Wayne Frederick, Bansal, Akash, Brooks, John Welsford, Kasamsetty, Kishore Ven
• Granted Patent: US 9,818,463 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1647 with interleaved bank access
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

Claims

1-20. -20. (canceled)

21. A method of operation within a memory control component, the method comprising:

outputting a sequence of command/address values via a command/address bus coupled in common to respective command/address inputs of first and second memory components;

asserting, at respective times, a first chip-select signal that enables the first memory component to sample a first command/address value in the sequence of command/address values and a second chip-select signal that enables the second memory component to sample a second command/address value in the sequence of command address values;

outputting first and second timing signals to the first and second memory components, respectively, the first timing signal to control a first sampling instant at which the first memory component samples the first command/address value and the second timing signal to control a second sampling instant at which the second memory component samples the second command/address value; and

establishing a timing offset between the first and second timing signals that compensates at least for a difference between respective first and second timing signal propagation delays within the first and second memory components, the first timing signal propagation delay corresponding to a time interval between arrival of the first timing signal at the first memory component and the first sampling instant, and the second timing signal propagation delay corresponding to a time interval between arrival of the second timing signal at the second memory component and the second sampling instant.

22. The method of claim 21 further comprising updating the timing offset between the first and second timing signals to compensate for independent and non-uniform changes in the first and second timing signal propagation delays that have occurred after establishing the timing offset.

23. The method of claim 21 wherein at least one of the first and second timing signal propagation delays exceeds a bit time on the command/address bus.

24. The method of claim 21 wherein establishing a timing offset between the first and second timing signals that compensates at least for the difference between respective first and second timing signal propagation delays within the first and second memory components comprises establishing a timing offset that also compensates for a difference between first and second command/address propagation times, the first command/address propagation time corresponding to a time required for the first command/address value to propagate via the command/address bus from the memory control component to the first memory component and the second command/address propagation time corresponding to a time required for the second command/address value to propagate via the command/address bus from the memory control component to the second memory component.

25. The method of claim 21 wherein outputting the first and second timing signals to the first and second memory components comprises outputting the first timing signal to the first memory component via a first timing signal link and outputting the second timing signal to the second memory component via a second timing signal link, and wherein establishing a timing offset between the first and second timing signals that compensates at least for the difference between respective first and second timing signal propagation delays within the first and second memory components comprises establishing a timing offset that also compensates for a difference between first and second timing link propagation times, the first timing link propagation time corresponding to a time required for the first timing signal to propagate via the first timing signal link from the memory control component to the first memory component and the second timing link propagation time corresponding to a time required for the second timing signal to propagate via the second timing signal link from the memory control component to the second memory component.

26. The method of claim 21 wherein establishing the timing offset between the first and second timing signals that compensates at least for the difference between the first and second timing signal propagation delays comprises independently determining respective output times for the first and second timing signals that compensate, respectively, for the first and second timing signal propagation delays.

27. The method of claim 21 wherein:

asserting a first chip-select signal that enables the first memory component to sample the first command/address value comprises asserting the first chip-select signal to enable a first plurality of memory components to sample the first command/address value, the first memory component being a constituent of the first plurality of memory components and the first plurality of memory components constituting a first memory rank; and

asserting a second chip-select signal that enables the second memory component to sample the first command/address value comprises asserting the second chip-select signal to enable a second plurality of memory components to sample the second command/address value, the second memory component being a constituent of the second plurality of memory components and the second plurality of memory components constituting a second memory rank.

28. The method of claim 21 wherein establishing a timing offset between the first and second timing signals that compensates at least for the difference between the first and second timing signal propagation delays comprises executing a timing calibration operation to determine respective first and second phase offsets of the first and second timing signals relative to a reference timing signal.

29. The method of claim 21 wherein outputting the sequence of command/address values via the command/address bus coupled in common to respective command/address inputs of the first and second memory components comprises outputting the sequence of command/address values via a first command/address bus, the method further comprising:

outputting a command/address value via a second command/address bus coupled to the first memory component but not the second memory component; and

outputting a command/address value via a third command/address bus coupled to the second memory component but not the first memory component.

30. The method of claim 21 wherein outputting first and second timing signals comprises outputting first and second strobe signals.

31. A memory control component comprising:

a command/address interface to output a sequence of command/address values via a command/address bus coupled in common to respective command/address inputs of first and second memory components;

a chip-select interface to assert, at respective times, a first chip-select signal that enables the first memory component to sample a first command/address value in the sequence of command/address values and a second chip-select signal that enables the second memory component to sample a second command/address value in the sequence of command address values; and

timing circuitry to;

output first and second timing signals to the first and second memory components, respectively, the first timing signal to control a first sampling instant at which the first memory component samples the first command/address value and the second timing signal to control a second sampling instant at which the second memory component samples the second command/address value;

establish a timing offset between the first and second timing signals that compensates at least for a difference between respective first and second timing signal propagation delays within the first and second memory components, the first timing signal delay corresponding to a time interval between arrival of the first timing signal at the first memory component and the first sampling instant, and the second timing signal delay corresponding to a time interval between arrival of the second timing signal at the second memory component and the second sampling instant.

32. The memory control component of claim 31 wherein the timing circuitry is further to update the timing offset between the first and second timing signals to compensate for independent and non-uniform changes in the first and second timing signal propagation delays that have occurred after establishing the timing offset.

33. The memory control component of claim 31 wherein at least one of the first and second timing signal propagation delays exceeds a bit time on the command/address bus.

34. The memory control component of claim 31 wherein the timing circuitry to establish a timing offset between the first and second timing signals that compensates at least for the difference between respective first and second timing signal propagation delays within the first and second memory components comprises circuitry to establish a timing offset that also compensates for a difference between first and second command/address propagation times, the first command/address propagation time corresponding to a time required for the first command/address value to propagate via the command/address bus from the memory control component to the first memory component and the second command/address propagation time corresponding to a time required for the second command/address value to propagate via the command/address bus from the memory control component to the second memory component.

35. The memory control component of claim 31 wherein the timing circuitry to output the first and second timing signals to the first and second memory components comprises:

a first output driver to output the first timing signal to the first memory component via a first timing signal link;

a second output driver to output the second timing signal to the second memory component via a second timing signal link; and

wherein the timing circuitry to establish a timing offset between the first and second timing signals that compensates at least for the difference between respective first and second timing signal propagation delays within the first and second memory components comprises circuitry to establish a timing offset that also compensates for a difference between first and second timing link propagation times, the first timing link propagation time corresponding to a time required for the first timing signal to propagate via the first timing signal link from the memory control component to the first memory component and the second timing link propagation time corresponding to a time required for the second timing signal to propagate via the second timing signal link from the memory control component to the second memory component.

36. The memory control component of claim 31 wherein the timing circuitry to establish the timing offset between the first and second timing signals that compensates at least for the difference between the first and second timing signal propagation delays comprises circuitry to independently determine respective output times for the first and second timing signals that compensate, respectively, for the first and second timing signal propagation delays.

37. The memory control component of claim 31 wherein:

the chip-select interface to assert the first chip-select signal that enables the first memory component to sample the first command/address value comprises output circuitry to assert the first chip-select signal to enable a first plurality of memory components to sample the first command/address value, the first memory component being a constituent of the first plurality of memory components and the first plurality of memory components constituting a first memory rank; and

the chip-select interface to assert the second chip-select signal that enables the second memory component to sample the second command/address value comprises output circuitry to assert the second chip-select signal to enable a second plurality of memory components to sample the second command/address value, the second memory component being a constituent of the second plurality of memory components and the second plurality of memory components constituting a second memory rank.

38. The memory control component of claim 31 wherein the timing circuitry to establish the timing offset between the first and second timing signals that compensates at least for the difference between the first and second timing signal propagation delays comprises circuitry to execute a timing calibration operation to determine respective first and second phase offsets of the first and second timing signals relative to a reference timing signal.

39. An integrated circuit (IC) package comprising:

first and second memory ICs;

a command/address bus coupled in common to the first and second memory ICs;

first and second chip-select links coupled respectively to the first and second memory ICs;

first and second timing signal links coupled respectively to the first and second memory ICs; and

a memory control IC having;

a command/address interface to output a sequence of command/address values via the command/address bus;

a chip-select interface to assert at respective times (i) a first chip-select signal via the first chip-select link to enable the first memory component to sample a first command/address value in the sequence of command/address values, and (ii) a second chip-select signal via the second chip-select link to enable the second memory component to sample a second command/address value in the sequence of command address values; and

timing circuitry to;

output first and second timing signals to the first and second memory components via the first and second timing signal links, respectively, the first timing signal to control a first sampling instant at which the first memory component samples the first command/address value and the second timing signal to control a second sampling instant at which the second memory component samples the second command/address value;

establish a timing offset between the first and second timing signals that compensates at least for a difference between respective first and second timing signal propagation delays within the first and second memory components, the first timing signal delay corresponding to a time interval between arrival of the first timing signal at the first memory component and the first sampling instant, and the second timing signal delay corresponding to a time interval between arrival of the second timing signal at the second memory component and the second sampling instant.

40. The IC package of claim 39 wherein the memory control IC and the first and second memory ICs are disposed in a stacked-die configuration.