Hardware Monitor to Verify Memory Units

• US 20170133104A1
• Filed: 11/01/2016
• Published: 05/11/2017
• Est. Priority Date: 11/11/2015
• Status: Active Grant

• Current Assignee: Imagination Technologies Limited (Imagination Technologies Group Ltd.)
• Original Assignee: Imagination Technologies Limited (Imagination Technologies Group Ltd.)
• Inventors: Darbari, Ashish, Singleton, Iain
• Granted Patent: US 10,580,511 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.

Claims

1. A hardware monitor configured to verify operation of an instantiation of a memory unit defined in a hardware design, the hardware monitor comprising:

detection logic configured to monitor one or more control signals of the instantiation of the memory unit to detect writes to a symbolic address of the instantiation of the memory unit and reads of the symbolic address of the instantiation of the memory unit, wherein the symbolic address is a variable that represents each possible address value of the instantiation of the memory unit which causes a formal verification tool to assess each of the possible address values; and

assertion verification logic configured to verify a formal assertion that establishes that when the detection logic detects a read of the symbolic address that occurs after one or more writes to the symbolic address, read data corresponding to the read of the symbolic address matches write data corresponding to the one or more writes to the symbolic address.

2. The hardware monitor of claim 1, further comprising a seen symbolic write register and wherein the detection logic is further configured to, in response to detecting a write to the symbolic address, determine if write data corresponding to the write to the symbolic address matches symbolic data, and in response to determining the write data matches the symbolic data, set the seen symbolic write register.

3. The hardware monitor of claim 2, further comprising a symbolic read request register and wherein the detection logic is further configured to, in response to detecting a read of the symbolic address when the seen symbolic write register is set, set the symbolic read request register;

and

wherein the assertion verification logic is configured to verify the assertion by, in response to determining the seen symbolic write register is set and the symbolic read request register is set, comparing the read data corresponding to the read of the symbolic address to the symbolic data.

4. The hardware monitor of claim 3, wherein the assertion verification logic is further configured to output an error message in response to determining the read data corresponding to the read of the symbolic address does not match the symbolic data.

5. The hardware monitor of claim 3, further comprising a symbolic mask register, and wherein the detection logic is configured to, in response to detecting a write of the symbolic data to the symbolic address, record in the symbolic mask register which particular bits of a memory block were written to;

and

wherein the assertion verification logic is configured to combine each of the read data corresponding to the read of the symbolic address and the symbolic data with the data in the symbolic mask register prior to comparing the read data corresponding to the read of the symbolic address and the symbolic data.

6. The hardware monitor of claim 1, further comprising:

a symbolic read request register, and wherein the detection logic is further configured to, in response to detecting a read of the symbolic address, set the symbolic read request register; and

a last written data register, and wherein the detection logic is further configured to, in response to detecting a write to the symbolic address, store write data corresponding to the write to the symbolic address in the last written data register.

7. The hardware monitor of claim 6, wherein the assertion verification logic is configured to verify the assertion by, in response to determining the symbolic read request register is set, comparing the read data corresponding to the read of the symbolic address to the write data in the last written data register.

8. The hardware monitor of claim 7, wherein the assertion verification logic is configured to output an error message in response to determining the read data corresponding to the read of the symbolic address does not match the write data in the last written data register.

9. The hardware monitor of claim 7, further comprising an initialised register, and wherein the detection logic is configured to, in response to detecting a write to the symbolic address, update the initialised register to indicate which particular bits of a memory block at the symbolic address have been written to at least once.

10. The hardware monitor of claim 9, wherein the assertion verification logic is configured to combine each of the read data corresponding to the read of the symbolic address and the write data in the last written data register with the data in the initialised register prior to comparing the read data corresponding to the read of the symbolic address and the write data in the last written data register.

11. The hardware monitor of claim 3, further comprising a seen symbolic read register, and wherein the detection logic is further configured to, monitor the one or more control signals to detect that read data corresponding to the read of the symbolic address has been output, and in response to detecting that read data corresponding to the read of the symbolic address has been output, set the seen symbolic read register.

12. The hardware monitor of claim 11, wherein the assertion verification logic is further configured to perform the comparison only if the seen symbolic read register is set.

13. The hardware monitor of claim 1, wherein the memory unit implements one or more of:

multiple access ports, partial reads and writes, pipelining, and clock gating.

14. The hardware monitor of claim 1, wherein the hardware monitor is embodied in hardware on an integrated circuit.

15. A test system configured to verify a hardware design for a memory unit, the test system comprising:

the hardware monitor as set forth in claim 1; and

a formal verification tool configured to use the hardware monitor to verify the assertion is true for the hardware design for each of the possible address values of the symbolic address.

19. A computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the system to manufacture a hardware monitor as set forth in claim 1.

16. The test system of claim 16, further comprising a configuration application program interface configured to identify the one or more control signals of the memory unit to be monitored by the detection logic based on a type of the memory unit, a configuration of the memory unit or both the type of the memory unit and the configuration of the memory unit.

17. A method of verifying operation of an instantiation of a memory unit defined by a hardware design, the method comprising:

monitoring, using detection logic, one or more control signals of the instantiation of the memory unit to detect writes to a symbolic address of the instantiation of the memory unit, wherein the symbolic address is a variable that represents each possible address value of the instantiation of the memory unit which causes a formal verification tool to assess each of the possible address values;

monitoring, using detection logic, one or more control signals of the instantiation of the memory unit to detect reads of the symbolic address of the instantiation of the memory unit; and

verifying operation of the instantiation of the memory unit, using assertion verification logic, by verifying a formal assertion that establishes that when a read of the symbolic address occurs after one or more writes to the symbolic address, read data corresponding to the read of the symbolic address matches write data corresponding to the one or more writes to the symbolic address.

18. Computer readable code adapted to perform the steps of the method set forth in claim 17 when the code is run on a computer.

20. A hardware monitor configured to verify a hardware design which defines operation of a unit in a computing system, the hardware monitor comprising:

detection logic configured to monitor one or more control signals of an instantiation of the unit to detect indications of the operation of the instantiation of the unit; and

assertion verification logic configured to verify the hardware design by verifying an assertion that the detection logic detects indications which are indicative of correct operation of the instantiation of the unit.