BACKGROUND MEMORY TEST APPARATUS AND METHODS

• US 20170133106A1
• Filed: 11/09/2016
• Published: 05/11/2017
• Est. Priority Date: 11/09/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Langadi, Saya Goud, Viswanathan Pillai, Prasanth
• Granted Patent: US 10,062,451 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 2029/1806 Address conversion or mapping, i.e. logical to physical address
• CPC Class Codes: G11C 2029/4002 Comparison of products, i.e. test results of chips or with golden chip
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/32 Serial access; Scan testing
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/093 CRC update after modification of the information word

Abstract

A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (“BGMTA”)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a “golden CRC.” If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.

Claims

1. An on-chip background memory test apparatus, comprising:

a memory test scheduler co-located on a semiconductor die with a central processing unit (“

CPU”

) communicatively coupled to a memory array via a system bus; and

a data fetch sequencer coupled to the memory test scheduler, the data fetch sequencer to access the memory array at times when the system bus is idle.

2. The on-chip background memory test apparatus of claim 1, the memory array structured with a data word length including a data field portion and at least one of a parity bit or a plurality of error correction code (“

ECC”

) bits.

3. The on-chip background memory test apparatus of claim 1, further comprising:

a memory controller coupled to the data fetch sequencer to address a data word from the memory array in response to address and control commands generated by the data fetch sequencer at the system bus.

4. The on-chip background memory test apparatus of claim 3, the memory controller further comprising:

a parity logic portion of the memory controller to exert a parity error interrupt to the CPU if the memory controller detects a parity error in a data word addressed in response to the commands generated by the data fetch sequencer.

5. The on-chip background memory test apparatus of claim 1, the data fetch sequencer further comprising:

a data fetch state machine coupled to a control bus portion of the system bus, the data fetch state machine to generate a bus request command to the memory controller and to enable an address word at an address bus portion of the system bus in response to a bus grant signal received from the memory controller and to repeat the bus request, bus grant and address enablement sequence for each address of a block of addresses associated with the memory array.

6. The on-chip background memory test apparatus of claim 5, the data fetch sequencer further comprising:

a current address register coupled to the data fetch state machine to store the address word; and

a bus driver logic module coupled to the current address register to present the address word to the address bus.

7. The on-chip background memory test apparatus of claim 5, the data fetch sequencer further comprising:

a current block register set coupled to the data fetch state machine to store memory address boundary values corresponding to a block of the memory array to be tested and to provide the boundary values to the data fetch state machine.

8. The on-chip background memory test apparatus of claim 7, the current block register set further comprising:

a block starting address register; and

a block size register.

9. The on-chip background memory test apparatus of claim 1, further comprising:

a watchdog timer coupled to the data fetch sequencer to generate a background memory test apparatus servicing interrupt to the CPU if the data fetch sequencer fails to complete all accesses to a memory block to be tested within a first predetermined amount of time or if a second predetermined amount of time between an exertion of a bus request signal and a receipt of a bus grant signal is exceeded.

10. The on-chip background memory test apparatus of claim 1, the memory test scheduler comprising:

at least one scheduler register set to store a test start time and a memory block boundary-determining subset of values;

a real-time clock (“

RTC”

) to generate a value corresponding to a current time-of-day; and

a word comparator coupled to the scheduler register set and to the RTC to generate a load command to load the memory block boundary-determining subset of values into the data fetch sequencer current block register set.

11. The on-chip background memory test apparatus of claim 10, the word comparator comprising:

a negated output bitwise exclusive OR logic module; and

an AND gate coupled to the exclusive OR logic module to generate the load command.

12. An on-chip background memory test apparatus, comprising:

a data fetch sequencer co-located on a semiconductor die with a central processing unit (“

CPU”

) communicatively coupled to a known-state memory array via a system bus, the data fetch sequencer to access the known-state memory array at times when the system bus is idle; and

a cyclic redundancy code (“

CRC”

) block test logic module coupled to the data fetch sequencer to receive a block of data words, to calculate an intermediate CRC value as each data word is received, to compare a final cumulative CRC value to a known data block CRC value associated with the block of data words after a last data word of the block is received, and to generate a CRC error interrupt request to the CPU if the final cumulative CRC value does not match the known data block CRC value.

13. The on-chip background memory test apparatus of claim 12, the known-state memory being at least one of a read-only memory fabricated to include a known data set, a programmable read-only memory programmed with a known data set, or a read/write memory to be written with a known data set.

14. The on-chip background memory test apparatus of claim 12, the CRC block test logic module comprising:

a cumulative CRC calculator communicatively coupled to the known-state memory to calculate the final cumulative CRC value;

at least one known memory block CRC register coupled to the CRC calculator to store the known data block CRC value; and

a binary word comparator coupled to the cumulative CRC calculator and to the known memory block CRC register to compare the final cumulative CRC value to the known data block CRC value and to generate the CRC error interrupt request to the CPU if the final cumulative CRC value does not match the known data block CRC value.

15. The on-chip background memory test apparatus of claim 12, the CRC block test logic module further comprising:

an intermediate result register portion of the cumulative CRC calculator to store the intermediate CRC value calculated as each data word is received.

16. The on-chip background memory test apparatus of claim 12, further comprising:

a memory test scheduler coupled to the data fetch sequencer to initiate testing of at least one block of a known-state memory array at a predetermined time.

17. An on-chip background memory test apparatus, comprising:

a memory test scheduler co-located on a semiconductor die with a central processing unit (“

CPU”

) communicatively coupled to a plurality of memory arrays via a system bus;

a data fetch sequencer coupled to the memory test scheduler, the data fetch sequencer to access the memory arrays at times when the system bus is idle; and

a cyclic redundancy code (“

CRC”

) block test logic module coupled to the data fetch sequencer to receive a block of data words, to calculate a cumulative CRC value as each data word is received, to compare a final CRC value to a known CRC value associated with the block of data words after a last data word of the block is received, and to generate a CRC error interrupt request to the CPU if the final CRC value does not match the known CRC value.

18. The on-chip background memory test apparatus of claim 17, the plurality of memory arrays including at least one parity-type memory array, at least one ECC type memory array, and/or at least one known-state type memory array.

19. The on-chip background memory test apparatus of claim 17, further including:

a plurality of bus mastering devices, each bus mastering device having a bus mastering direct memory access (“

DMA”

) controller; and

a bus mastering bus controller to grant access by each of the bus mastering devices to the system bus based upon a priority pre-assigned to each bus mastering device, the background memory test apparatus having a lowest priority.

20. The on-chip background memory test apparatus of claim 17, further including:

a watchdog timer coupled to the data fetch sequencer to generate a background memory test apparatus servicing interrupt to the CPU if the data fetch sequencer fails to complete all accesses to a memory block to be tested within a first predetermined amount of time or if a second predetermined amount of time between an exertion of a bus request signal and a receipt of a bus grant signal is exceeded.