BACKGROUND MEMORY TEST APPARATUS AND METHODS
First Claim
1. An on-chip background memory test apparatus, comprising:
- a memory test scheduler co-located on a semiconductor die with a central processing unit (“
CPU”
) communicatively coupled to a memory array via a system bus; and
a data fetch sequencer coupled to the memory test scheduler, the data fetch sequencer to access the memory array at times when the system bus is idle.
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Abstract
A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (“BGMTA”)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a “golden CRC.” If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.
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Citations
20 Claims
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1. An on-chip background memory test apparatus, comprising:
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a memory test scheduler co-located on a semiconductor die with a central processing unit (“
CPU”
) communicatively coupled to a memory array via a system bus; anda data fetch sequencer coupled to the memory test scheduler, the data fetch sequencer to access the memory array at times when the system bus is idle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An on-chip background memory test apparatus, comprising:
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a data fetch sequencer co-located on a semiconductor die with a central processing unit (“
CPU”
) communicatively coupled to a known-state memory array via a system bus, the data fetch sequencer to access the known-state memory array at times when the system bus is idle; anda cyclic redundancy code (“
CRC”
) block test logic module coupled to the data fetch sequencer to receive a block of data words, to calculate an intermediate CRC value as each data word is received, to compare a final cumulative CRC value to a known data block CRC value associated with the block of data words after a last data word of the block is received, and to generate a CRC error interrupt request to the CPU if the final cumulative CRC value does not match the known data block CRC value. - View Dependent Claims (13, 14, 15, 16)
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17. An on-chip background memory test apparatus, comprising:
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a memory test scheduler co-located on a semiconductor die with a central processing unit (“
CPU”
) communicatively coupled to a plurality of memory arrays via a system bus;a data fetch sequencer coupled to the memory test scheduler, the data fetch sequencer to access the memory arrays at times when the system bus is idle; and a cyclic redundancy code (“
CRC”
) block test logic module coupled to the data fetch sequencer to receive a block of data words, to calculate a cumulative CRC value as each data word is received, to compare a final CRC value to a known CRC value associated with the block of data words after a last data word of the block is received, and to generate a CRC error interrupt request to the CPU if the final CRC value does not match the known CRC value. - View Dependent Claims (18, 19, 20)
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Specification