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BACKGROUND MEMORY TEST APPARATUS AND METHODS

  • US 20170133106A1
  • Filed: 11/09/2016
  • Published: 05/11/2017
  • Est. Priority Date: 11/09/2015
  • Status: Active Grant
First Claim
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1. An on-chip background memory test apparatus, comprising:

  • a memory test scheduler co-located on a semiconductor die with a central processing unit (“

    CPU”

    ) communicatively coupled to a memory array via a system bus; and

    a data fetch sequencer coupled to the memory test scheduler, the data fetch sequencer to access the memory array at times when the system bus is idle.

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