FAN-OUT SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME

• US 20170133309A1
• Filed: 10/27/2016
• Published: 05/11/2017
• Est. Priority Date: 11/10/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: KIM, Sun Ho, KIM, Ji Hoon, KOOK, Seung Yeop, JEONG, Sung Won, AHN, Ha Young, SEO, Shang Hoon
• Granted Patent: US 10,128,179 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3512 Cracking

Abstract

A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.

Claims

1. A fan-out semiconductor package comprising:

a first interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other;

a semiconductor chip disposed on the first interconnection member; and

an encapsulant encapsulating at least portions of the semiconductor chip,

wherein a center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.

2. The fan-out semiconductor package of claim 1, further comprising a passivation layer disposed on a side of the first insulating layer on which the first pad is disposed and having an opening exposing at least a portion of the first pad,

wherein the center line of the first via is different from that of the opening.

3. The fan-out semiconductor package of claim 2, further comprising a connection terminal disposed in the opening of the passivation layer and connected to the first pad,

wherein the center line of the first via is different from that of the connection terminal.

4. The fan-out semiconductor package of claim 3, wherein the passivation layer is a solder resist layer, and the connection terminal is a solder ball.

5. The fan-out semiconductor package of claim 1, wherein the first interconnection member includes a first region corresponding to a region in which the semiconductor chip is disposed, and a second region enclosing the first region, and

the first pad, the second pad, and the first via are disposed in a corner portion of the second region.

6. The fan-out semiconductor package of claim 1, wherein the first interconnection member includes a first region corresponding to a region in which the semiconductor chip is disposed, and a second region enclosing the first region, and

the first pad, the second pad, and the first via are disposed in a corner portion of the first region and a portion of the second region enclosing the corner portion of the first region.

7. The fan-out semiconductor package of claim 1, wherein the first interconnection member includes a first region corresponding to a region in which the semiconductor chip is disposed, and a second region enclosing the first region, and

the first pad, the second pad, and the first via are disposed in an outermost portion of the second region.

8. The fan-out semiconductor package of claim 1, wherein the first interconnection member includes a first region corresponding to a region in which the semiconductor chip is disposed, and a second region enclosing the first region, and

the first pad, the second pad, and the first via are disposed in an outermost portion of the first region.

9. The fan-out semiconductor package of claim 1, wherein the center line of the first via is off the center line of the first pad toward an outer edge of the semiconductor chip package.

10. The fan-out semiconductor package of claim 1, further comprising a second interconnection member disposed on the first interconnection member and having a through-hole,

wherein the semiconductor chip is disposed in the through-hole of the second interconnection member.

11. The fan-out semiconductor package of claim 10, further comprising a through-wiring penetrating through the second interconnection member;

and

redistribution layers disposed on both surfaces of the second interconnection member,

wherein the through-wiring and the redistribution layers are electrically connected to the semiconductor chip.

12. The fan-out semiconductor package of claim 1, wherein the first interconnection member further includes a second insulating layer disposed on the first insulating layer and a second via formed in the second insulating layer,

the second pad connects the first and second vias to each other, and

the center line of the first via, a center line of the second via, and the center line of the second pad are different from each other.

13. The fan-out semiconductor package of claim 12, wherein the second pad has an area greater than that of a via pad disposed in other region of the first interconnection member.

14. The fan-out semiconductor package of claim 12, wherein the first interconnection member includes a first region corresponding to a region in which the semiconductor chip is disposed, and a second region enclosing the first region,

wherein the first via, the second via, and the second pad are disposed in a corner portion of the second region.

15. The fan-out semiconductor package of claim 12, wherein the first interconnection member includes a first region corresponding to a region in which the semiconductor chip is disposed, and a second region enclosing the first region, and

the first via, the second via, and the second pad are disposed in a corner portion of the first region and a portion of the second region enclosing the corner portion of the first region.

16. The fan-out semiconductor package of claim 12, wherein the first interconnection member includes a first region corresponding to a region in which the semiconductor chip is disposed, and a second region enclosing the first region, and

the first via, the second via, and the second pad are disposed in an outermost portion of the second region.

17. The fan-out semiconductor package of claim 12, wherein the first interconnection member includes a first region corresponding to a region in which the semiconductor chip is disposed, and a second region enclosing the first region, and

the first via, the second via, and the second pad are disposed in an outermost portion of the first region.

18. The fan-out semiconductor package of claim 12, wherein the first and second vias are disposed in a staggered form, a zigzag form, or a spiral form.

19. An electronic device comprising:

a board; and

a semiconductor chip package mounted on the board,

wherein the semiconductor chip package is the semiconductor chip package of claim 1.

20. Fan-out semiconductor package comprising:

an interconnection member including an insulating layer, first and third pads and second and fourth pads respectively disposed on opposite sides of the insulating layer, a first via penetrating the insulating layer and connecting the first and second pads to each other, and a second via penetrating the insulating layer and connecting the third and fourth pads to each other; and

a semiconductor chip disposed on the interconnection member and electrically connected to the first through fourth pads and the first and second vias of the interconnection member,

wherein a distance from the first and second pads and the first via to a center of the semiconductor chip is greater than a distance from the third and fourth pads and the second via to the center of the semiconductor chip, and

an average of an interval between a center line of the first via and a center line of the first pad and an interval of the center line of the first via and a center line of the second pad is greater than an average of an interval of a center line of the second via and a center line of the third pad and an interval of the center line of the second via and a center line of the fourth pad.

21. The fan-out semiconductor package of claim 20, wherein the center line of the first via is off at least one of the center line of the first pad and the center line of the second pad in a direction away from the center of the semiconductor chip, and

the center line of the second via coincides with at least one of the center line of the third pad and the center line of the fourth pad.

22. The fan-out semiconductor package of claim 20, further comprising a passivation layer disposed on a side of the insulating layer on which the first and third pads are disposed and having first and second openings respectively exposing portions of the first and third pads,

wherein an interval between the center line of the first via and a center line of the first opening is greater than an interval of the center line of the second via and a center line of the second opening.

23. The fan-out semiconductor package of claim 22, further comprising first and second connection terminals disposed in the first and second openings of the passivation layer, respectively,

wherein the passivation layer is a solder resist layer, and the first and second connection terminals are solder balls.

24. The fan-out semiconductor package of claim 20, wherein the interconnection member further includes fifth and sixth pads and respectively disposed on the opposite sides of the insulating layer, and a third via penetrating the insulating layer and connecting the fifth and sixth pads to each other,

the third and fourth pads and the second via are disposed in a region between two regions where the first and second pads and the first via, and the fifth and sixth pads and the third via are disposed, respectively and

an average of an interval between a center line of the third via and a center line of the fifth pad and an interval of the center line of the third via and a center line of the sixth pad is greater than the average of the interval of the center line of the second via and the center line of the third pad and the interval of the center line of the second via and the center line of the fourth pad.

25. Fan-out semiconductor package comprising:

an interconnection member including a plurality of insulating layers and a plurality of first vias each penetrating one of the plurality of insulating layers and electrically connected to each other through a plurality of first wiring patterns respectively formed on the plurality of the insulating layers; and

a semiconductor chip disposed on the interconnection member and electrically connected to the plurality of first vias,

wherein center lines of any two of the plurality of first vias directly electrically connected to one of the plurality of first wiring patterns are out of alignment.

26. The fan-out semiconductor package of claim 25, wherein the interconnection member further includes a plurality of second vias each penetrating one of the plurality of insulating layers and electrically connected to each other through a plurality of second wiring patterns respectively formed on the plurality of the insulating layers, and

an average of all the intervals between center lines of any two of the plurality of first vias that are directly connected to any one of the plurality of first wiring patterns is greater than an average of all the intervals between center lines of any two of the plurality of second vias that are directly connected to any one of the plurality of second wiring patterns.

27. The fan-out semiconductor package of claim 26, wherein a distance from the plurality of first vias to a center of the semiconductor chip is greater than a distance from the plurality of second vias to the center of the semiconductor chip.

28. The fan-out semiconductor package of claim 27, wherein the interconnection member further includes a plurality of third vias each penetrating one of the plurality of insulating layers and electrically connected to each other through a plurality of third wiring patterns respectively formed on the plurality of the insulating layers, and

an average of intervals between center lines of any two of the plurality of third vias that are directly connected to any one of the plurality of third wiring patterns is greater than the average of all the intervals between the center lines of any two of the plurality of second vias that are directly connected to any one of the plurality of second wiring patterns.

29. The fan-out semiconductor package of claim 28, wherein the plurality of first vias and the plurality of third vias are disposed on opposite sides of the plurality of second vias.