Bump Structure for Yield Improvement

• US 20170133346A1
• Filed: 01/23/2017
• Published: 05/11/2017
• Est. Priority Date: 07/25/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiu, Tzu-Wei, Wang, Tzu-Yu, Hou, Shang-Yun, Jeng, Shin-Puu, Chen, Hsien-Wei, Teng, Hung-An, Wu, Wei-Cheng
• Granted Patent: US 10,056,347 B2
• Time in Patent Office: Days
• CPC Class Codes: B23K 1/0016 Brazing of electronic components
• CPC Class Codes: C23C 14/165 by cathodic sputtering
• CPC Class Codes: C23C 14/34 Sputtering
• CPC Class Codes: C23C 18/32 Coating with nickel, cobalt or mixtures thereof with phosphorus or boron C23C18/50 takes precedence
• CPC Class Codes: C23C 18/42 Coating with noble metals
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05582 Two-layer coating
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/10125 Reinforcing structures
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/119 Methods of manufacturing bump connectors involving a specific sequence of method steps
• CPC Class Codes: H01L 2224/11903 using different masks
• CPC Class Codes: H01L 2224/13005 Structure
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13019 : at the bonding interface of the bump connector, i.e. on the surface of the bump connector
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13076 : being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13562 : On the entire exposed surface of the core
• CPC Class Codes: H01L 2224/13564 : Only on the bonding interface of the bump connector
• CPC Class Codes: H01L 2224/13583 : Three-layer coating
• CPC Class Codes: H01L 2224/13644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/16058 : being non uniform along the bump connector
• CPC Class Codes: H01L 2224/16059 : comprising protrusions or indentations
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16148 : the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/8112 : Aligning
• CPC Class Codes: H01L 2224/81141 : Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81345 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81365 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

Claims

1. A method of forming a device, the method comprising:

forming a first non-flat portion on a first bump;

covering the first bump with a first material;

forming a second non-flat portion on a second bump, the first non-flat portion having a same number of recesses as the second non-flat portion has projections;

covering the second non-flat portion with a second material;

aligning the recesses of the first non-flat portion with the projections of the second non-flat portion; and

reflowing the first material and the second material, thereby forming a bond between the first non-flat portion and the second non-flat portion.

2. The method of claim 1, wherein the first material is solder and the second material is electroless nickel electroless palladium immersion gold.

3. The method of claim 1, wherein the second non-flat portion comprises a flat shoulder along a periphery.

4. The method of claim 1, wherein forming the second non-flat portion on the second bump comprises:

forming a first patterned mask over a passivation layer, the passivation layer having a first opening, the first opening exposing a contact pad, the first patterned mask having a second opening, the contact pad being exposed in the second opening;

forming a first conductive element in the second opening, the first conductive element extending above an upper surface of the passivation layer;

removing the first patterned mask;

forming a second patterned mask over the passivation layer, the second patterned mask having a third opening, a width of the third opening being greater than a width of the first conductive element; and

forming a second conductive element over the first conductive element in the third opening, the first conductive element and the second conductive element forming the second non-flat portion on the second bump.

5. The method of claim 4, wherein forming the first non-flat portion on the first bump comprises:

forming a first patterned mask over a passivation layer, the passivation layer having a first opening, the first opening exposing a contact pad, the first patterned mask having a second opening, the contact pad and an upper surface of the passivation layer being exposed in the second opening; and

forming a first conductive element in the second opening, the first conductive element extending above an upper surface of the passivation layer, an upper surface of the first conductive element having a second recess within the first opening, the first conductive element forming the first non-flat portion on the first bump.

6. The method of claim 1, wherein after reflowing a first projection of the projections extends into a first recess of the recesses.

7. A method of forming a device, the method comprising:

forming a passivation layer over a substrate, the substrate having a contact pad, the passivation layer having a first opening, the first opening exposing the contact pad;

forming a first patterned mask over the passivation layer, the first patterned mask having a second opening, the contact pad being exposed in the second opening;

forming a first conductive element in the second opening, the first conductive element extending above an upper surface of the passivation layer;

removing the first patterned mask;

forming a second patterned mask over the passivation layer, the second patterned mask having a third opening, a width of the third opening being greater than a width of the first conductive element;

forming a second conductive element over the first conductive element in the third opening, the first conductive element and the second conductive element forming a first bump having a first projection; and

attaching the first bump to a second bump, the second bump having a first recess, wherein after the attaching the first projection is aligned with the first recess.

8. The method of claim 7, further comprising forming an insulating layer along sidewalls of the first opening.

9. The method of claim 8, wherein the insulating layer extends along an upper surface of the passivation layer.

10. The method of claim 8, wherein the second conductive element extends over an upper surface of the insulating layer.

11. The method of claim 8, wherein a width of the third opening is less than a width of the insulating layer.

12. The method of claim 7, further comprising, prior to forming the first patterned mask, sputtering a conductive layer over the passivation layer, the first patterned mask being on the conductive layer.

13. The method of claim 12, wherein the conductive layer comprises a Ti layer and a Cu layer.

14. A method of forming a device, the method comprising:

forming a passivation layer over a first substrate, the first substrate having a contact pad, the passivation layer having a first opening, the first opening exposing the contact pad;

forming a first patterned mask over the passivation layer, the first patterned mask having a second opening, the contact pad and an upper surface of the passivation layer being exposed in the second opening;

forming a first conductive element in the second opening, the first conductive element extending above an upper surface of the passivation layer, an upper surface of the first conductive element having a first recess within the first opening, the first conductive element forming a first bump;

removing the first patterned mask;

forming a second conductive element over the first conductive element, the second conductive element having a lower reflow temperature than the first conductive element;

aligning a first projection of a second bump on a second substrate to the first recess of the first bump, the second bump having a third conductive element; and

reflowing the second conductive element and the third conductive element.

15. The method of claim 14, wherein forming the passivation layer comprises forming a first passivation layer and a second passivation layer over the first passivation layer.

16. The method of claim 15, wherein sidewalls of the first passivation layer are continuous with sidewalls of the second passivation layer.

17. The method of claim 14, further comprising, prior to forming the first patterned mask, sputtering a conductive layer on the passivation layer, the first patterned mask being formed on the conductive layer.

18. The method of claim 17, further comprising, after removing the first patterned mask, removing exposed portions of the conductive layer.

19. The method of claim 18, wherein the second conductive element extends along sidewalls of the first patterned mask.

20. The method of claim 14, wherein the second conductive element is interposed between sidewalls of the first opening.