NANOSHEET ISOLATION FOR BULK CMOS NON-PLANAR DEVICES

• US 20170133459A1
• Filed: 11/09/2015
• Published: 05/11/2017
• Est. Priority Date: 11/09/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pranatharthiharan, Balasubramanian, Ok, Injo, Seo, Soon-Cheon, Surisetty, Charan Veera Venkata Satya
• Granted Patent: US 9,871,099 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate including a first device region and a second device region, wherein first trench isolation structures surround said first and second device regions and extend below first and second pedestal portions of said semiconductor substrate;

a first semiconductor material fin stack located above said first pedestal portion of said semiconductor substrate;

a second semiconductor material fin stack located above said second pedestal portion of said semiconductor substrate; and

second trench isolation structures located at ends of each first semiconductor material fin stack and said second semiconductor material fin stack, wherein a portion of one of said second trench isolation structures is located directly between a bottommost surface of said first semiconductor material fin stack and said first pedestal portion of said semiconductor substrate and another of said second trench isolation structures is located directly between a bottommost surface of said second semiconductor material fin stack and said second pedestal portion of said semiconductor substrate.

2. The semiconductor structure of claim 1, wherein an isolation spacer is located on upper portion of sidewall surfaces of said first trench isolation structure and surrounding an upper portion of said second trench isolation structure.

3. The semiconductor structure of claim 1, wherein a topmost surface of said first and second semiconductor material fin stacks is coplanar with a topmost surface of said first trench isolation structure.

4. The semiconductor structure of claim 3, wherein each of said first and second semiconductor material fin stacks comprises from bottom to top, alternating layers of silicon and a silicon germanium alloy, wherein each layer of silicon germanium alloy is sandwiched by a lower layer of silicon and an upper layer of silicon.

5. The semiconductor structure of claim 1, wherein said first trench isolation structure has depth that is greater than a depth of said second trench isolation structure.

6. The semiconductor structure of claim 1, further comprising at least one functional gate structure straddling over at least one of said first and second semiconductor material fin stacks.

7. The semiconductor structure of claim 6, wherein a portion of said at least one functional gate structure is located between a neighboring pair of first trench isolation structures, and another portion of said at least one functional gate structure is located above said neighboring pair of first trench isolation structures.

8. The semiconductor structure of claim 1, wherein said semiconductor substrate is a bulk semiconductor substrate.

9. The semiconductor structure of claim 1, further comprising a first functional gate structure straddling over a portion of said first semiconductor fin stack, and a second functional gate structure straddling over another portion of said first semiconductor fin stack and a portion of said second semiconductor fin stack.

10. The semiconductor structure of claim 1, wherein said portion of said one of said second trench isolation structures that is located directly between said bottommost surface of said first semiconductor material fin stack and said first pedestal portion of said semiconductor substrate and said portion of said another of said second trench isolation structures directly between said bottommost surface of said second semiconductor material fin stack contacts a sidewall surface of one of said first trench isolation structures.

11. A method of forming a semiconductor structure, said method comprising:

providing a first semiconductor nanowire material stack located in a first device region of a semiconductor substrate and a second semiconductor nanowire material stack located in a second device region of the semiconductor substrate, wherein said first semiconductor nanowire material stack is located on a first sacrificial silicon germanium alloy portion and said second semiconductor nanowire material stack is located on a second sacrificial silicon germanium alloy portion and wherein a first trench isolation structure surrounds each of said first and second semiconductor nanowire material stacks;

forming an isolation spacer along an upper portion of each first trench isolation structure;

removing an entirety of said first and second sacrificial silicon germanium alloy portions to provide an opening within said first and second device regions, each opening having a portion directly beneath said first and second semiconductor nanowire material stacks; and

forming a second trench isolation structure within each opening, wherein a portion of said second trench isolation structure with each opening extends directly beneath said first and second semiconductor nanowire material stacks.

12. The method of claim 11, further comprising:

forming a first semiconductor fin stack from said first semiconductor nanowire stack and a second semiconductor fin stack from said second semiconductor nanowire stack.

13. The method of claim 12, further comprising:

forming a first functional gate structure straddling over a portion of said first semiconductor fin stack, and

forming a second functional gate structure straddling over another portion of said first semiconductor fin stack and a portion of said second semiconductor fin stack.

14. The method of claim 13, wherein a portion of said first functional gate structure and second functional gate structure is located between a portion of a neighboring pair of said first trench isolation structures.

15. The method of claim 11, wherein each of said first and second semiconductor nanowire structures comprises from bottom to top, alternating layers of silicon and a silicon germanium alloy, wherein each layer of silicon germanium alloy is sandwiched by a lower layer of silicon and an upper layer of silicon.

16. The method of claim 11, wherein said forming said isolation spacer comprises:

forming a sacrificial trench isolation structure having a second depth between a neighboring pair of first trench isolation structures in said first and second device regions; and

etching through a portion of said sacrificial trench isolation structures.

17. The method of claim 11, wherein said first and second sacrificial silicon germanium alloy portions are located on a pedestal portion of said semiconductor substrate.

18. The method of claim 17, wherein a portion of each first trench isolation structure extends into a portion of said semiconductor substrate.

19. The method of claim 11, wherein said removing said entirety of said first and second sacrificial silicon germanium alloy portions comprises an etching process that is selective in removing a silicon germanium alloy.

20. The method of claim 11, wherein each first trench isolation structure has a topmost surface that is coplanar with a topmost surface of each second trench isolation structure and a topmost surface of said first and second semiconductor nanowire stack structures.