LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

• US 20170133475A1
• Filed: 10/15/2015
• Published: 05/11/2017
• Est. Priority Date: 06/23/2015
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: MIN, Jian
• Granted Patent: US 9,923,075 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A low temperature poly-silicon thin film transistor and a manufacturing method thereof are disclosed. The method includes forming an active layer on a base substrate, forming an ohmic contact layer on the active layer through an atomic layer deposition process, and forming a source electrode and a drain electrode on the ohmic contact layer. The ohmic contact layer includes a plurality of conductive ionic layers and a plurality of monocrystalline silicon layers/poly-silicon layers. The source electrode and the drain electrode are in contact with the active layer through the ohmic contact layer.

Claims

1. A method of manufacturing a low temperature poly-silicon thin film transistor, comprising:

forming an active layer on a base substrate;

forming an ohmic contact layer on the active layer through an atomic layer deposition process, the ohmic contact layer comprising a plurality of conductive ionic layers and a plurality of monocrystalline silicon layers/poly-silicon layers; and

forming a source electrode and a drain electrode on the ohmic contact layer, the source electrode and the drain electrode being in contact with the active layer through the ohmic contact layer.

2. The method according to claim 1, wherein the forming an ohmic contact layer comprises:

forming a gate insulating layer, a gate electrode and an interlayer insulating layer on the active layer, the interlayer insulating layer being located between the gate electrode and the source and drain electrodes;

forming via holes in the interlayer insulating layer, the gate insulating layer and the active layer through a dry etching process; and

forming the conductive ionic layers and the monocrystalline silicon layers/poly-silicon layers in the via holes through the atomic layer deposition process.

3. The method according to claim 1, wherein a thickness of the ohmic contact layer is not less than 100 Å

and not more than 2000 Å

.

4. The method according to claim 1, wherein ions of the conductive ionic layers comprise boron ions or phosphor ions.

5. The method according to claim 4, wherein an ion doping concentration of the conductive ionic layer is in the range of 10¹⁴/cm³ to 10¹⁸/cm³.

6. The method according to claim 5, wherein the ions of the conductive ionic layers are boron ions and a threshold for the ion doping concentration is 10¹⁵/cm³.

7. The method according to claim 1, wherein the base substrate is a flexible substrate.

8. The method according to claim 7, wherein the ohmic contact layer is formed on the active layer through the atomic layer deposition process below 300°

C.

13. The method according to claim 2, wherein ions of the conductive ionic layers comprise boron ions or phosphor ions.

14. The method according to claim 13, wherein an ion doping concentration of the conductive ionic layer is in the range of 10¹⁴/cm³ to 10¹⁸/cm³.

15. The method according to claim 14, wherein the ions of the conductive ionic layers are boron ions and a threshold for the ion doping concentration is 10¹⁵/cm³.

16. The method according to claim 3, wherein ions of the conductive ionic layers comprise boron ions or phosphor ions.

17. The method according to claim 16, wherein an ion doping concentration of the conductive ionic layer is in the range of 10¹⁴/cm³ to 10¹⁸/cm³.

18. The method according to claim 17, wherein the ions of the conductive ionic layers are boron ions and a threshold for the ion doping concentration is 10¹⁵/cm³.

9. A low temperature poly-silicon thin film transistor, comprising:

a base substrate;

an active layer arranged on the base substrate;

an ohmic contact layer arranged on the active layer, the ohmic contact layer comprising a plurality of conductive ionic layers and a plurality of monocrystalline silicon layers/poly-silicon layers, and the ohmic contact layer being formed on the active layer through an atomic layer deposition process; and

a source electrode and a drain electrode arranged on the ohmic contact layer, and being in contact with the active layer through the ohmic contact layer.

10. The low temperature poly-silicon thin film transistor according to claim 9, wherein

ions of the conductive ionic layers comprise boron ions or phosphor ions, and

an ion doping concentration of the conductive ionic layer is in the range of 10¹⁴/cm³ to 10¹⁸/cm³.

11. The low temperature poly-silicon thin film transistor according to claim 10, wherein the ions of the conductive ionic layers are boron ions and a threshold for the ion doping concentration is 10¹⁵/cm³.

12. The low temperature poly-silicon thin film transistor according to claim 9, wherein

the base substrate is a flexible substrate, and

the ohmic contact layer is formed on the active layer through the atomic layer

deposition process below 300°

C.

19. The low temperature poly-silicon thin film transistor according to claim 10, wherein

the base substrate is a flexible substrate, and

the ohmic contact layer is formed on the active layer through the atomic layer deposition process below 300°

C.

20. The low temperature poly-silicon thin film transistor according to claim 11, wherein

the base substrate is a flexible substrate, and

the ohmic contact layer is formed on the active layer through the atomic layer deposition process below 300°

C.