MANUFACTURING METHOD OF FLIP-CHIP STRUCTURE OF III GROUP SEMICONDUCTOR LIGHT EMITTING DEVICE

• US 20170133549A1
• Filed: 05/05/2016
• Published: 05/11/2017
• Est. Priority Date: 05/05/2015
• Status: Active Grant

• Current Assignee: Xiangneng Hualei Optoelectronic Co., Ltd.
• Original Assignee: Xiangneng Hualei Optoelectronic Co., Ltd.
• Inventors: Xu, Shuncheng, Liang, Zhiyong, Cai, Bingjie
• Granted Patent: US 10,147,849 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/153 in a repetitive configuration, e.g. LED bars
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/10 with a light reflecting structure, e.g. semiconductor Bragg reflector
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/42 Transparent materials
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

This disclosure refers to a manufacturing method of a flip-chip structure of III group semiconductor light emitting device. The manufacturing method includes steps of: growing a substrate, a buffer layer, an N type nitride semiconductor layer, an active layer and a P type nitride semiconductor layer sequentially from bottom to top to form an epitaxial structure, depositing a transparent conductive layer; defining an isolation groove with the yellow light etching process, depositing a first insulation layer structure, depositing a P type contact metal and N type contact metal, depositing a second insulation layer structure, depositing a flip-chip P type electrode and flip-chip N type electrode, then removing the photo resist by using of the stripping process to get a wafer; thinning, dicing, separating, measuring and sorting the wafer. In this disclosure, structure of the first insulation layer structure which is formed by the Prague reflective layer, the metal layer and the multilayer of oxide insulation, acts as a reflector structure and an insulation layer to replace the flip-chip reflector structure design and the first insulation layer, so that a metal protective layer can be omitted.

Claims

1. A manufacturing method of a flip-chip structure of III group semiconductor light emitting device, comprising the steps of:

growing a substrate, a buffer layer, an N type nitride semiconductor layer, an active layer and a P type nitride semiconductor layer sequentially from bottom to top to form an epitaxial structure, wherein the top surface of the epitaxial structure is the top surface of the P type nitride semiconductor layer;

depositing a transparent conductive layer on the top surface of the P type nitride semiconductor, defining a pattern of a linear convex mesa by using of a yellow light etching process, etching the transparent conductive layer, the P type nitride semiconductor layer and the active layer;

exposing the N type nitride semiconductor layer; and

shrinking the transparent conductive layer with etching solution;

finally removing a photo resist to get the linear convex mesa whose top surface has the transparent conductive layer, wherein the linear convex mesa comprises a first top surface, a side surface and a second top surface, the first top surface and the second top surface individually connects with the side surface to form a L shape structure, the first top surface of the linear convex mesa being the top surface of the P type nitride semiconductor layer, the second top surface of the linear convex mesa being the top surface of the N type nitride semiconductor layer;

in this step, individually forming the transparent conductive layer and the linear convex mesa, that is, not forming the transparent conductive layer and the linear convex mesa in the same etching step, but forming the transparent conductive layer at first and forming the linear convex mesa on the next, or forming the linear convex mesa at first and forming the transparent conductive layer on the next;

defining an isolation groove with the yellow light etching process, then etching the N type nitride semiconductor layer and the buffer layer to expose the substrate, and finally removing the photo resist;

or the isolation groove not be located in the flip-chip structure of the III group semiconductor light emitting device, or the isolation groove be located in any steps behind this step;

depositing a first insulation layer structure which is formed by a Prague reflective layer, a metal layer and a multilayer of oxide insulation;

wherein the Prague reflective layer is deposited at first, then a pattern on the metal layer is defined by a yellow light stripping process, the metal layer is deposited, and the photo resist is removed to get the metal layer by a stripping process, and the multilayer of oxide insulation is deposited, and then a connection pattern between a P type contact metal and the transparent conductive layer and a contact pattern between an N type contact metal and the second top surface of the linear convex mesa are defined by using of the yellow light etching process, then an connecting pattern between the multilayer of the oxide insulation and the Prague reflective layer is continuously etched, and finally the photo resist is removed to get the first insulation layer structure;

defining a pattern of the P type contact metal and a pattern of the N type contact metal by the yellow light etching process, and depositing the P type contact metal and the N type contact metal in the mean time, and then the photo resist is removed with the stripping process to get the P type contact metal and the N type contact metal, therein, a bottom side of the P type contact metal is located on the surface of the transparent conductive layer and the first insulation layer structure, and a bottom side of the N type contact metal is located on the second top surface of the linear convex mesa and the surface of the first insulation layer structure;

depositing a second insulation layer structure, wherein a pattern is defined by the yellow light etching process, the pattern is used for accessing the P type contact metal and the N type contact metal with an opening, then an opening pattern of the second insulation layer structure is etched, and finally the photo resist is removed;

defining a pattern of a flip-chip P type electrode and a flip-chip N type electrode by the yellow light stripping process, wherein the flip-chip P type electrode and the flip-chip N type electrode is deposited, then the photo resist is removed by use of the stripping process to get a wafer;

thinning, dicing, separating, measuring and sorting the wafer.

2. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device of claim 1, wherein the first insulation layer structure is located on the first top surface, the side surface, the second top surface, the transparent conductive layer and the optional isolation groove.

3. The manufacturing method a of flip-chip structure of III group semiconductor light emitting device of claim 1, wherein the structure of the Prague reflective layer comprises silicon dioxide and titanium dioxide, or is comprising of silicon dioxide and tantalic oxide, or is comprising of silicon dioxide and niobium oxide.

4. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device of claim 3, wherein the thickness of the silicon dioxide is in a range of 30-1000 nm, the thickness of the titanium dioxide is in a range of 10-200 nm, the thickness of the tantalic oxide is in a range of 10-200 nm, and the thickness of the niobium oxide is in a range of 10-200 nm.

5. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device of claim 3, wherein the Prague reflective layer is 3.5 pairs of silicon dioxide/titanium dioxide/silicon dioxide/titanium dioxide/silicon dioxide, or 3.5 pairs of silicon dioxide/tantalic oxide/silicon dioxide/tantalic oxide/silicon dioxide, or 3.5 pairs of silicon dioxide/niobium oxide/silicon dioxide/niobium oxide/silicon dioxide.

6. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device of claim 1, wherein the first insulation layer structure is formed by the Prague reflective layer, the metal layer, the Prague reflective layer, the metal layer and the multilayer of the oxide insulation, a bottom side of the metal layer is located on the top surface of the Prague reflective layer of the first insulation layer structure, and/or is located in the multilayer of the oxide insulation layer of the first insulation layer structure.

7. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device of claim 6, wherein the metal layer material is comprising of at least one of silver, aluminum, silver indium, platinum, nickel and titanium, therein a thickness of the silver, the aluminum, the indium and the platinum is respectively in a range of 50-500 nm, and a thickness of the nickel and the titanium is respectively in a range of 0.3-30 nm.

8. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device of claim 6, wherein the multilayer of the oxide insulation layer is formed by at least two combinations of aluminum oxide, silicon dioxide, titanium dioxide, tantalic oxide, niobium oxide, silicon oxide and silicon nitride, a thickness of each layer of the multilayer of the oxide insulation is in a range of 30-200 nm.

9. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device of claim 1, wherein the P type contact metal comprises a P type linear electrode and the P type connection metal;

the bottom side of the P type linear electrode is located on the surface of the first insulation layer structure and the transparent conductive layer;

the bottom side of the P type connection metal is located on the surface of first insulation layer structure;

and the N type contact metal comprises an N type linear electrode and the N type connection metal, a bottom side of the N type linear electrode is located on the first insulation layer structure and the second top surface, a bottom side of the N type connection metal is located on the surface of the first insulation layer structure.

10. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device of claim 1, wherein the structure of the P type contact metal and N type contact metal has the same structure which are a single metal layer or a multilayer of metal layer, and both sequentially comprise a first Ni layer, an Al layer, a second Ni layer, an Au layer and a third Ni layer from inner to outer, or sequentially comprise a Ti layer, an Al layer, the second Ni layer, an Au layer and the third Ni layer from inner to outer, or sequentially comprise the Ti layer, the Al layer and the third Ni layer from inner to outer, or sequentially comprise the first Ni layer, the Al layer, the second Ni layer, a Pt layer, the Au layer and the third layer Ni from inner to outer, or sequentially comprise an Cr layer, the Pt layer, the Au layer and the third Ni layer from inner to outer, or sequentially comprise the first Ni layer, the Al layer and the third Ni layer, or sequentially comprise an Rh layer, therein, a thickness of the Rh layer is in a range of 50-3000 nm, a thickness of the first Ni layer is in a range of 0.3-300 nm, a thickness of the Al layer is in a range of 50-300 nm, a thickness of the second Ni layer is in a range of 10-300 nm, a thickness of the Pt layer is in a range of 10-300 nm, a thickness of the Au layer is in a range of 10-3000 nm, a thickness of the third Ni layer is in a range of 0.3-300 nm.

11. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device of claim 1, wherein the second insulation layer is disposed on the top surface of the first insulation layer, the top surface of the P type contact metal, and the top surface of the N type contact metal.

12. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device of claim 11, wherein the second insulation layer structure is a multilayer of the oxide insulation, the multilayer of the oxide insulation is formed by at least two of the combinations of aluminum oxide, silicon dioxide, titanium dioxide, tantalic oxide, niobium oxide, silicon oxide and silicon nitride, a thickness of each layer of the multilayer of the oxide insulation is in a range of 30-2000 nm.

13. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device of claim 1, wherein the bottom side of the flip-chip P type electrode is deposed on the surface of the P type contact metal and the second insulation layer, the bottom side of the flip-chip N type electrode is deposed on the surface of the N type contact metal and the second insulation layer structure.

14. The manufacturing method of a flip-chip structure of III group semiconductor light emitting device as defined as claimed 13, wherein the flip-chip P type electrode and the flip-chip N type electrode has the same structure, both sequentially comprise a Ti layer and a second Ni layer and an Au layer from inner to outer, or sequentially comprise a middle Cr layer, a Pt layer, an Au layer, a second Ni layer a Pt layer, a second Ni layer and an AuSn layer from inner to outer, or sequentially comprise a first Ni layer and an Al layer, the second Ni layer and the Au layer from inner to outer, or sequentially comprise the middle Cr layer, the Pt layer and the Au layer from inner to outer, or sequentially comprise the first Ni layer, the Al layer, the middle Cr layer and the second Ni layer and the Au layer from inner to outer, or sequentially comprise the first Ni layer, the Al layer, the second Ni layer, the Pt layer and the Au layer from inner to outer, therein a thickness of the first Ni layer is in a range of 0.4-3 nm, a thickness of the second Ni layer is in a range of 10-300 nm, a thickness of the Ti layer is in a range of 10-300 nm, a thickness of the Al layer is in a range of 50-300 nm, a thickness of the Au layer is in a range of 20-3000 nm, a thickness of the middle Cr layer is in a range of 10-300 nm, a thickness of the Pt layer is in a range of 10-300 nm, and a thickness of the AuSn layer is in a range of 1000-5000 nm.