DISPLAY WITH SURFACE MOUNT EMISSIVE ELEMENTS

• US 20170133550A1
• Filed: 01/19/2017
• Published: 05/11/2017
• Est. Priority Date: 10/31/2014
• Status: Active Grant

• Current Assignee: Elux Inc.
• Original Assignee: Elux Inc.
• Inventors: Schuele, Paul J., Ulmer, Kurt, Lee, Jong-Jan, Sasaki, Kenji
• Granted Patent: US 9,825,202 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/30 containing only elements of Group III and Group V of the Periodic Table
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A surface mount emissive element is provided with a top surface and a bottom surface. A first electrical contact is formed exclusively on the top surface, and a second electrical contact is formed exclusively on the top surface. A post extends from the bottom surface. An emissive display is also provided made from surface mount emissive elements and an emissions substrate. The emissions substrate has a top surface with a first plurality of wells formed in the emissions substrate top surface. Each well has a bottom surface, sidewalls, a first electrical interface formed on the bottom surface, and a second electrical interface formed on the bottom surface. The emissions substrate also includes a matrix of column and row conductive traces forming a first plurality of column/row intersections, where each column/row intersection is associated with a corresponding well. A first plurality of emissive elements populates the wells.

Claims

1. A surface mount emissive element comprising:

a top surface;

a bottom surface;

a first electrical contact formed exclusively on the top surface;

a second electrical contact formed exclusively on the top surface; and

,

a post extending from the bottom surface.

4. The surface mount emissive element of claim 1 wherein the first electrical contact is configured as a ring;

wherein the first semiconductor layer and MQW layer are a stack underlying the first electrical contact, in the shape of a ring;

wherein the second electrical contact is formed within a first electrical contact ring perimeter; and

,

wherein the second semiconductor layer has a disk shape with a center portion underlying the second electrical contact.

5. The surface mount emissive element of claim 4 further comprising:

a moat formed between the first electrical contact ring and the second electrical contact; and

,

an electrical insulator filling the moat.

6. The surface mount emissive element of claim 1 wherein the second electrical contact is configured as a ring;

wherein the second semiconductor layer has a disk shape with a perimeter underlying the second electrical contact ring;

wherein the first electrical contact is formed within a second electrical contact ring perimeter; and

,

wherein the first semiconductor layer and MQW layer are a stack underlying the first electrical contact.

7. The surface mount emissive element of claim 6 further comprising:

a moat formed between the first electrical contact ring and the second electrical contact; and

,

an electrical insulator filling the moat.

8. The surface mount emissive element of claim 1 wherein the top surface is planar;

and,

wherein the bottom surface is planar.

9. The surface mount emissive element of claim 1 wherein the top surface is bi-planar with a first level and a second level;

wherein the first electrical contact is formed on the first level of the top surface; and

,

wherein the second electrical contact is formed on the second level of the top surface.

10. The surface mount emissive element of claim 1 further comprising:

a plurality of posts extending from the bottom surface.

11. The surface mount emissive element of claim 1 wherein the first and second electrical contacts are solder-coated.

2. The surface mount emissive element is a surface mount light emitting diode (SMLED) comprising:

a first semiconductor layer, with a dopant selected from a first group consisting of an n-dopant or a p-dopant;

a second semiconductor layer, with the unselected dopant from the first group; and

,

a multiple quantum well (MQW) layer interposed between the first semiconductor layer and the second semiconductor layer.

3. The surface mount emissive element of claim 2 wherein the first semiconductor layer and second semiconductor layer are a material selected from the group consisting of gallium nitride (GaN) and aluminum gallium indium phosphide (AlGaInP).

12. An emissive display comprising:

an emissions substrate comprising;

a top surface;

a first plurality of wells formed in the emissions substrate top surface, each well comprising a bottom surface, sidewalls, a first electrical interface formed on the bottom surface, and a second electrical interface formed on the bottom surface;

a matrix of column and row conductive traces forming a first plurality of column/row intersections, where each column/row intersection is associated with a corresponding well;

a first plurality of surface mount emissive elements populating the wells, each emissive element comprising;

a top surface overlying a corresponding well bottom surface;

a bottom surface;

a first electrical contact formed on the top surface and connected to a corresponding well first electrical interface;

a second electrical contact formed on the top surface and connected to a corresponding well second electrical interface; and

,

a post extending from the bottom surface.

13. The emissive display of claim 12 further comprising:

a color modifier overlying each emissive element bottom surface; and

,

a liquid crystal display (LCD) substrate overlying the color modifier.

14. The emissive display of claim 12 wherein the emissive elements are surface mount light emitting diodes (SMLEDs), each SMLED comprising:

a first semiconductor layer, with a dopant selected from a first group consisting of an n-dopant or a p-dopant;

a second semiconductor layer, with the unselected dopant from the first group; and

,

a multiple quantum well (MQW) layer interposed between the first semiconductor layer and the second semiconductor layer.

15. The emissive display of claim 14 wherein the first and second semiconductor layers are selected from the group consisting of gallium nitride (GaN) and aluminum gallium indium phosphide (AlGaInP).

16. The emissive display of claim 15 further comprising:

a second plurality of first color modifiers overlying the bottom surfaces of a corresponding second plurality of SMLEDs, where the second plurality is less than the first plurality;

a second plurality of second color modifiers overlying the bottom surfaces of a corresponding second plurality of SMLEDs, where the second color is different than the first color.

17. The emissive display of claim 16 further comprising:

a second plurality of light diffusers overlying the bottom surfaces of a corresponding second plurality of SMLEDs with no overlying color modifier.

18. The emissive display of claim 17 further comprising:

a second plurality of pixel regions, each pixel region comprising a SMLED with an overlying first color modifier, a SMLED with an overlying second color modifier, and a SMLED with no overlying color modifier; and

,

wherein the first color is green, the second color is red, and wherein the SMLED with no overlying color modifier emits a blue light.

19. The emissive display of claim 15 further comprising:

a second plurality of red color modifiers overlying the bottom surfaces of a corresponding second plurality of SMLEDs, where the second plurality is less than the first plurality;

a third plurality of light diffusers overlying the bottom surfaces of a corresponding third plurality of SMLEDs with no overlying color modifier, where the third plurality is less than the first plurality and equal to twice the second plurality; and

,

a second plurality of pixel regions, each pixel region comprising a SMLED with an overlying red color modifier, a blue color SMLED with no overlying color modifier, and a green color SMLED with no color modifier.

20. The emissive display of claim 14 wherein the first electrical contact of each SMLED is configured as a ring with a first diameter;

wherein the first semiconductor layer and MQW layer of each SMLED are a stack overlying the first electrical contact, in the shape of a ring;

wherein the second electrical contact of each SMLED is formed within a first electrical contact ring perimeter;

wherein the second semiconductor layer of each SMLED has a disk shape with a center portion overlying the second electrical contact;

wherein each well first electrical interface is configured as a partial ring with the first diameter, and having a mouth opening; and

,

wherein each well second electrical interface is configured as a trace extending into the mouth of a corresponding first electrical interface partial ring.

21. The emissive display of claim 14 wherein the second electrical contact of each SMLED is configured as a ring with a first diameter;

wherein the second semiconductor layer of each SMLED has a disk shape with a perimeter overlying the second electrical contact ring;

wherein the first electrical contact of each SMLED is formed within a second electrical contact ring perimeter;

wherein the first semiconductor layer and MQW layer of each SMLED are a stack overlying the first electrical contact;

wherein each well second electrical interface is configured as a partial ring with the first diameter, and having a mouth opening; and

,

wherein each well first electrical interface is configured as a trace extending into the mouth of a corresponding second electrical interface partial ring.

22. The emissive display of claim 12 wherein each emissive element top surface is planar;

and,

wherein each well bottom surface is planar.

23. The emissive display of claim 12 wherein each emissive element top surface is bi-planar with a first level and a second level;

wherein each emissive element first electrical contact is formed on the first level of the top surface;

wherein each emissive element second electrical contact is formed on the second level of the top surface;

wherein each well bottom surface is bi-planar with a first level and a second level;

wherein each well first electrical interface is formed on the well bottom first level; and

,

wherein each well second electrical interface is formed on the well bottom second level.

24. The emissive display of claim 12 further comprising:

a first plurality of active matrix (AM) drive circuits, each drive circuit connected to a corresponding column/row intersection, and connected to the first electrical interface of a corresponding well; and

,

a network of reference voltage traces connected to the second electrical interface of each well.

25. The emissive display of claim 12 wherein the matrix of column and row traces form a passive matrix (PM) with the column trace of each column/row intersection connected to the first electrical interface of a corresponding well, and the row trace of each column/row intersection connected to the second electrical interface of each well.

26. The emissive display of claim 12 further comprising:

a solder coating applied to elements selected from the group consisting of the first and second electrical contacts of the emissive elements, the first and second electrical interfaces in the wells, or both the first and second electrical contacts of the emissive elements and the first and second electrical interfaces in the wells.