Delay Line System and Switching Apparatus with Embedded Attenuators

• US 20170134012A1
• Filed: 10/20/2016
• Published: 05/11/2017
• Est. Priority Date: 05/16/2014
• Status: Active Grant

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Alidio, Raul Inocencio, Bacon, Peter
• Granted Patent: US 10,056,889 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/28 Modifications for introducing a time delay before switching modifications to provide a choice of time-intervals for executing more than one switching action H03K17/296
• CPC Class Codes: H03K 17/284 in field effect transistor switches
• CPC Class Codes: H03K 17/76 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence

Abstract

Systems, methods, and apparatus for reducing standing wave reflections between delay line modules are described. The delay line modules include semiconductor switches, particularly MOSFET switches fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates and embedded attenuators.

Claims

1. A monolithically integrated switch comprising:

an input port configured to carry the input signal;

a plurality of switches configured to provide a plurality of conduction paths;

a first output port and a second output port;

a first conduction path of the plurality of conduction paths between the input port and the first output port, the first conduction path comprising a first attenuator block comprising one or more shunting resistors coupled to one or more series connected switches of the plurality of switches;

a second conduction path of the plurality of conduction paths between the input port and the second output port;

a first shunting path of the plurality of conduction paths between the first output port and a reference potential;

a second shunting path of the plurality of conduction paths between the second output port and the reference potential;

wherein;

a low impedance or high impedance of a conduction path of the plurality of conduction paths is selectively provided by one or more switches of the plurality of switches based on a mode of operation of the switch;

during a first mode of operation of the switch, the first conduction path and the second shunting path are low impedance conduction paths, and the second conduction path and the first shunting path are high impedance conduction paths, and

during a second mode of operation of the switch, the second conduction path and the first shunting path are low impedance conduction paths, and the first conduction path and the second shunting path are high impedance conduction paths.

2. The monolithically integrated switch of claim 1, wherein the second conduction path further comprises a second attenuator block comprising one or more shunting resistors coupled to one or more series connected switches of the plurality of switches.

3. The monolithically integrated switch of claim 1 or claim 2, wherein the one or more shunting resistors of the first attenuator block and/or the second attenuator block are coupled to respective common nodes of the one or more series connected switches

4. The monolithically integrated switch of claim 1 or claim 2, wherein the one or more shunting resistors of the first attenuator block and/or the second attenuator block comprises one shunting resistor coupled to a respective common node of two series connected switches of the one or more series connected switches

5. The monolithically integrated switch of claim 1 or claim 2, wherein resistance values of the one or more shunting resistors of the first attenuator block and/or second attenuator block are a same value resistance.

6. The monolithically integrated switch of claim 1 or claim 2, wherein resistance values of the one or more shunting resistors of the first attenuator block and/or the second attenuator block are configured to provide an output impedance seen at a respective output port of the first output port and the second output port to substantially match a value of a load impedance coupled to said output port, based on a value of an ON resistance of the one or more series connected switches.

7. The monolithically integrated switch of claim 1 or claim 2, wherein resistance values of the one or more shunting resistors of the first attenuator block and/or the second attenuator block are configured to adjust a characteristic impedance of a respective conduction path of the first conduction path and the second conduction path based on a value of an ON resistance of the one or more series connected switches.

8. The monolithically integrated switch of claim 1 or claim 2, wherein each of the first and the second shunting paths comprise one or more series connected switches of the plurality of the switches, a number of the one or more series connected switches being selected based on a desired voltage handling capability of the monolithically integrated switch.

9. The monolithically integrated switch of claim 8, wherein a switch of the plurality of switches is one of:

a) a metal-oxide field effect transistor (MOSFET), b) a metal-semiconductor field effect transistor (MESFET), c) a P-N diode, and d) a PIN diode.

10. The monolithically integrated switch of claim 9 fabricated using a technology comprising one of:

a) silicon on sapphire (SOS), b) silicon on insulator (SOI), c) bulk-silicon, and d) micro-electro-mechanical systems.

11. A delay line module comprising:

a first switch and a second switch, each of said first switch and second switch being the monolithically integrated switch of claim 2;

a first delay module coupled between the first output port of the first switch and the first output port of the second switch; and

a second delay module coupled between the second output port of the first switch and the second output port of the second switch.

12. The delay line module of claim 11, wherein during the first mode of operation of the first switch and the second switch, a low impedance path is provided between the input port of the first switch and the input port of the second switch through the first delay module, and during the second mode of operation of the first switch and the second switch, a low impedance path is provided between the input port of the first switch and the input port of the second switch through the second delay module.

13. The delay line module of claim 12, wherein the first delay module passes a signal with zero delay, and the second delay module passes a signal with a nominal delay, the nominal delay being one of:

a) a time delay (Δ

t), and b) a frequency independent phase shift (Δ

φ

).

27. A switched delay line module comprising a plurality of series connected delay line modules according to claim 11 or claim 21.

28. The switched delay line module of claim 27 monolithically integrated on a same integrated circuit.

29. The switched delay line module of claim 28 fabricated using a technology comprising one of:

a) silicon on sapphire (SOS), b) silicon on insulator (SOI), c) bulk-silicon, and d) micro-electro-mechanical systems.

14. A monolithically integrated switch comprising:

an input port configured to carry the input signal;

a plurality of switches configured to provide a plurality of conduction paths;

a plurality of output ports comprising a first output port, a second output port, . . . , and an n^th output port, n being an integer equal to or greater than three;

a first conduction path of the plurality of conduction paths between the input port and the first output port, the first conduction path comprising a first attenuator block comprising one or more shunting resistors coupled to one or more series connected switches of the plurality of switches;

a second conduction path of the plurality of conduction paths between the input port and the second output port;

. . . an n^th conduction path of the plurality of conduction paths between the input port and the n^th output port;

a first shunting path of the plurality of conduction paths between the first output port and a reference potential;

a second shunting path of the plurality of conduction paths between the second output port and the reference potential;

. . . and;

an n^th shunting path of the plurality of conduction paths between the n^th output port and the reference potential,

wherein;

a low impedance or high impedance of a conduction path of the plurality of conduction paths is selectively provided by one or more switches of the plurality of switches based on a mode i of operation of the switch, where i E [1, 2, . . . , n],

during the mode i of operation of the switch, the i^th conduction path is a low impedance conduction path and all p^th conduction paths, with p=[1, 2, . . . i−

1, i+1, . . . , n], are high impedance conduction paths, and

during the mode i of operation of the switch, the i^th shunting path is a high impedance conduction path and all p^th shunting paths, with p=[1, 2, . . . , i−

1, i+1, . . . , n], are low impedance conduction paths.

15. The monolithically integrated switch of claim 14, wherein at least the second conduction path of the plurality of conduction paths further comprises one or more shunting resistors coupled to one or more series connected switches of the plurality of switches.

16. The monolithically integrated switch of claim 14 or claim 15, wherein the one or more shunting resistors of the first attenuator block and/or the second attenuator block are coupled to respective common nodes of the one or more series connected switches.

17. The monolithically integrated switch of claim 14 or claim 15, wherein the one or more shunting resistors of the first attenuator block and/or the second attenuator block comprises one shunting resistor coupled to a respective common node of two series connected switches of the one or more series connected switches.

18. The monolithically integrated switch of claim 14, wherein each of the first, the second, . . . , and the n^th shunting paths comprise one or more series connected switches of the plurality of switches, a number of the one or more series connected switches being selected based on a desired voltage handling capability of the monolithically integrated switch.

19. The monolithically integrated switch of claim 14, wherein a switch of the plurality of switches is one of:

a) a metal-oxide field effect transistor (MOSFET), b) a metal-semiconductor field effect transistor (MESFET), c) a P-N diode, and d) a PIN diode.

20. The monolithically integrated switch of claim 19 fabricated using a technology comprising one of:

a) silicon on sapphire (SOS), b) silicon on insulator (SOI), c) bulk-silicon, and d) micro-electro-mechanical systems.

21. A delay line module comprising:

(i) a first switch and a second switch, the first switch and the second switch being the monolithically integrated switch of claim 15; and

(ii) a plurality of delay modules comprising;

a first delay module coupled between the first output port of the first switch and the first output port of the second switch;

a second delay module coupled between the second output port of the first switch and the second output port of the second switch;

. . . and;

an n^th delay module coupled between the n^th output port of the first switch and the n^th output port of the second switch.

22. The delay line module of claim 21, wherein during the mode i of operation of the first switch and the second switch, a low impedance path is provided between the input port of the first switch and the input port of the second switch through the i^th delay module.

23. The delay line module of claim 22, wherein the first delay module passes a signal with zero delay.

24. The delay line module of claim 22, wherein one or more delay modules of the first, second, . . . , n^th delay module pass a signal with a nominal delay, the nominal delay being one of:

a) a time delay (Δ

t), and b) a frequency independent phase shift (Δ

φ

).

25. The delay line module of claim 24, wherein a nominal delay of an i^th delay module of the one or more delay modules is different from a nominal delay of a p^th delay module of the one or more delay modules, wherein i is different from p.

26. The delay line module of claim 25, wherein:

for a), the nominal delay of the i^th delay module is equal to x<sup>i−

1</sup>*Δ

t, and the nominal delay of the p^th delay module is equal to x<sup>p−

1</sup>*Δ

t, where Δ

t is a fixed non zero delay and x is a non-zero number, and

for b), the nominal delay of the i^th delay module is equal to x<sup>i−

1</sup>*Δ

φ

, and the nominal delay of the p^th delay module is equal to x<sup>p−

1</sup>*Δ

φ

, where Δ

φ

is a fixed non zero frequency independent phase shift and x is a non-zero number.

30. A method for reducing input return loss in a monolithically integrated single pole double throw (SPDT) switch, the method comprising:

providing in a conduction path between a pole terminal and a first throw terminal of the SPDT integrated switch an attenuator block comprising one or more switches and one or more shunting resistors;

based on the providing, selecting a resistance value of the one or more shunting resistors based on an ON resistance of the one or more switches and a desired load impedance at the first throw terminal;

based on the selecting, decreasing an impedance value seen at the first throw terminal; and

based on the decreasing, substantially matching the impedance value seen at the first throw terminal to the desired load impedance, thereby reducing the input return loss at the first throw terminal.

31. The method of claim 30, further comprising fabricating the monolithically integrated SPDT switch using a technology comprising one of:

a) silicon on sapphire (SOS), b) silicon on insulator (SOI), c) bulk-silicon, and d) micro-electro-mechanical systems.

32. A monolithically integrated comprising:

(i) an input port configured to carry the input signal;

(ii) a first output port and a second output port;

(iii) a first conduction path between the input port and the first output port, comprising;

a first group of one or more series connected switches coupled between the input port and the first output port;

a first group of one or more shunting resistors coupled between the first group of one or more series connected switches and ground; and

a second group of one or more series connected switches coupled between the first output port and ground; and

(iv) a second conduction path between the input port and the second output port, comprising;

a third group of one or more series connected switches coupled between the input port and the second output port;

a second group of one or more shunting resistors coupled between the third group of one or more series connected switches and ground; and

a fourth group of one or more series connected switches coupled between the second output port and ground.

33. The monolithically integrated switch of claim 32, further comprising:

a first mode of operation wherein;

the first group of one or more series connected switches are ON;

the second group of one or more series connected switches are OFF;

the third group of one or more series connected switches are OFF; and

the fourth group of one or more series connected switches are ON;

and

a second mode of operation wherein;

the first group of one or more series connected switches are OFF;

the second group of one or more series connected switches are ON;

the third group of one or more series connected switches are ON; and

the fourth group of one or more series connected switches are OFF.

34. The monolithically integrated switch of claim 32, wherein a shunting resistor of the first group of one or more shunting resistors is connected to a common node of two series connected switches of the first group of one or more series connected switches.

35. The monolithically integrated switch of claim 32, wherein two shunting resistors of the first group of one or more shunting resistors are respectively connected to different nodes of a conduction path provided by one switch of the first group of one or more switches.