DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

• US 20170134049A1
• Filed: 12/29/2015
• Published: 05/11/2017
• Est. Priority Date: 11/05/2015
• Status: Abandoned Application

• Current Assignee: Epostar Electronics (Bvi) Corporation
• Original Assignee: Epostar Electronics (Bvi) Corporation
• Inventors: Hsiao, Yu-Hua, Chang, Hung-Chi, Yen, Heng-Lin
• Application Number:
  US14/981,965
• Publication Number:
  US 20170134049A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H03M 13/036 Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
• CPC Class Codes: H03M 13/116 Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• CPC Class Codes: H03M 13/1174 Parity-check or generator matrices built from sub-matrices representing known block codes such as, e.g. Hamming codes, e.g. generalized LDPC codes
• CPC Class Codes: H03M 13/6502 Reduction of hardware complexity or efficient processing
• CPC Class Codes: H03M 13/6505 Memory efficient implementations
• CPC Class Codes: H03M 13/6566 Implementations concerning memory access contentions

Abstract

A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: determining an offset threshold value and a corresponding check matrix; receiving response data from a rewritable non-volatile memory module and performing an iterative decoding process. The check matrix includes at least one sub-matrix group, each sub-matrix of the sub-matrix group has a default dimension, and the offset threshold value is less than a default dimension value corresponding to the default dimension In the iterative decoding process, several default groups in a data set are shifted, so as to obtain first shift groups, while an offset of each first shift group with respect to a corresponding group among the default groups is not over the default threshold value. Therefore, decoding reference data used in the iterative decoding process may be generated more efficiently.

Claims

1. A decoding method for a rewritable non-volatile memory module, comprising:

determining an offset threshold value and a check matrix corresponding to the offset threshold value, wherein the check matrix comprises at least one sub-matrix group, each sub-matrix of the at least one sub-matrix group has a default dimension, the offset threshold value is less than a default dimension value corresponding to the default dimension, and the at least one sub-matrix group comprises a first sub-matrix group;

transmitting a read command sequence, wherein the read command sequence instructs to read a physical unit of the rewritable non-volatile memory module;

receiving response data corresponding to the read command sequence; and

performing an iterative decoding process on the response data,

wherein the iterative decoding process comprises;

generating a data set corresponding to the response data, wherein the data set comprises a plurality of default groups;

shifting the default groups according to a plurality of sub-matrices belonging to the first sub-matrix group to obtain a plurality of first shift groups, wherein an offset of each shift group in the first shift groups with respect to a corresponding group among the default groups is not over the offset threshold value; and

generating a decoding reference data according to the first shift groups.

2. The decoding method according to claim 1, wherein the at least one sub-matrix group further comprises a second sub-matrix group,

wherein the iterative decoding process further comprises:

shifting the first shift groups according to a plurality of sub-matrices belonging to the second sub-matrix group to obtain a plurality of second shift groups, wherein an offset of each shift group in the second shift groups with respect to a corresponding group among the first shift groups is not over the offset threshold value; and

generating the decoding reference data according to the second shift groups.

3. The decoding method according to claim 1, wherein the decoding reference data is a syndrome set of a parity check procedure corresponding to a low density parity code (LDPC) algorithm.

4. The decoding method according to claim 1, wherein the decoding reference data is a syndrome weight set corresponding to a bit-flipping algorithm.

5. The decoding method according to claim 1, wherein the decoding reference data is a minimum value set of a min-sum algorithm corresponding to an LDPC algorithm.

6. The decoding method according to claim 1, wherein the offset threshold value is negatively correlated to a column weight of the check matrix,

wherein the column weight is corresponding to a total number of an element of 1 contained in a column of the check matrix.

7. The decoding method according to claim 6, wherein the offset threshold value is equal to or greater than a minimum threshold value obtained by dividing the default dimension value by the column weight.

8. A memory storage device, comprising:

a connection interface unit configured to couple to a host system;

a rewritable non-volatile memory module; and

a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module,

wherein the memory control circuit unit is configured to determine an offset threshold value and a check matrix corresponding to the offset threshold value, wherein the check matrix comprises at least one sub-matrix group, each sub-matrix of the at least one sub-matrix group has a default dimension, the offset threshold value is less than a default dimension value corresponding to the default dimension, and the at least one sub-matrix group comprises a first sub-matrix group,

wherein the memory control circuit unit is further configured to transmit a read command sequence, wherein the read command sequence instructs to read a physical unit of the rewritable non-volatile memory module,

wherein the memory control circuit unit is further configured to receive response data corresponding to the read command sequence,

wherein the memory control circuit unit is further configured to perform an iterative decoding process on the response data, wherein the iterative decoding process comprises;

generating a data set corresponding to the response data, wherein the data set comprises a plurality of default groups;

shifting the default groups according to a plurality of sub-matrices belonging to the first sub-matrix group to obtain a plurality of first shift groups, wherein an offset of each shift group in the first shift groups with respect to a corresponding group among the default groups is not over the offset threshold value; and

generating a decoding reference data according to the first shift groups.

9. The memory storage device according to claim 8, wherein the at least one sub-matrix group further comprises a second sub-matrix group,

wherein the iterative decoding process further comprises:

shifting the first shift groups according to a plurality of sub-matrices belonging to the second sub-matrix group to obtain a plurality of second shift groups, wherein an offset of each shift group in the second shift groups with respect to a corresponding group among the first shift groups is not over the offset threshold value; and

generating the decoding reference data according to the second shift groups.

10. The memory storage device according to claim 8, wherein the decoding reference data is a syndrome set of a parity check procedure corresponding to an LDPC algorithm.

11. The memory storage device according to claim 8, wherein the decoding reference data is a syndrome weight set corresponding to a bit-flipping algorithm.

12. The memory storage device according to claim 8, wherein the decoding reference data is a minimum value set of a min-sum algorithm corresponding to an LDPC algorithm.

13. The memory storage device according to claim 8, wherein the offset threshold value is negatively correlated to a column weight of the check matrix,

wherein the column weight is corresponding to a total number of an element of 1 contained in a column of the check matrix.

14. The memory storage device according to claim 13, wherein the offset threshold value is equal to or greater than a minimum threshold value obtained by dividing the default dimension value by the column weight.

15. A memory control circuit unit configured to control a rewritable non-volatile memory module, the memory control circuit unit comprising:

a host interface configured to couple to a host system;

a memory interface configured to couple to the rewritable non-volatile memory module;

an error checking and correcting circuit; and

a memory management circuit coupled to the host interface, the memory interface and the error checking and correcting circuit,

wherein the memory management circuit is configured to determine an offset threshold value and a check matrix corresponding to the offset threshold value, wherein the check matrix comprises at least one sub-matrix group, each sub-matrix of the at least one sub-matrix group has a default dimension, the offset threshold value is less than a default dimension value corresponding to the default dimension, and the at least one sub-matrix group comprises a first sub-matrix group,

wherein the memory management circuit is further configured to transmit a read command sequence, wherein the read command sequence instructs to read a physical unit of the rewritable non-volatile memory module,

wherein the memory management circuit is further configured to receive response data corresponding to the read command sequence,

wherein the error checking and correcting circuit is configured to perform an iterative decoding process on the response data, wherein the iterative decoding process comprises;

generating a data set corresponding to the response data, wherein the data set comprises a plurality of default groups;

shifting the default groups according to a plurality of sub-matrices belonging to the first sub-matrix group to obtain a plurality of first shift groups, wherein an offset of each shift group in the first shift groups with respect to a corresponding group among the default groups is not over the offset threshold value; and

generating a decoding reference data according to the first shift groups.

16. The memory control circuit unit according to claim 15, wherein the at least one sub-matrix group further comprises a second sub-matrix group,

wherein the iterative decoding process further comprises:

shifting the first shift groups according to a plurality of sub-matrices belonging to the second sub-matrix group to obtain a plurality of second shift groups, wherein an offset of each shift group in the second shift groups with respect to a corresponding group among the first shift groups is not over the offset threshold value; and

generating the decoding reference data according to the second shift groups.

17. The memory control circuit unit according to claim 15, wherein the decoding reference data is a syndrome set of a parity check procedure corresponding to an LDPC algorithm.

18. The memory control circuit unit according to claim 15, wherein the decoding reference data is a syndrome weight set corresponding to a bit-flipping algorithm.

19. The memory control circuit unit according to claim 15, wherein the decoding reference data is a minimum value set of a min-sum algorithm corresponding to an LDPC algorithm.

20. The memory control circuit unit according to claim 15, wherein the offset threshold value is negatively correlated to a column weight of the check matrix,

wherein the column weight is corresponding to a total number of an element of 1 contained in a column of the check matrix.

21. The memory control circuit unit according to claim 20, wherein the offset threshold value is equal to or greater than a minimum threshold value obtained by dividing the default dimension value by the column weight.

22. The memory control circuit unit according to claim 15, wherein the error checking and correcting circuit comprises:

at least one first temporary storage circuit configured to temporarily store a target group among the default groups;

a shift circuit coupled to at least one first temporary storage circuit and configured to shift the target group and output an shifted target group among the first shift groups corresponding to the target group;

at least one second temporary storage circuit coupled to the shift circuit and configured to temporarily store the shifted target group; and

at least one operation circuit coupled to the at least one second temporary storage circuit and configured to perform a logic operation on the shifted target group and generate the decoding reference data.