Memory System and Method for Improving Write Performance in a Multi-Die Environment

• US 20170139590A1
• Filed: 11/12/2015
• Published: 05/18/2017
• Est. Priority Date: 11/12/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Yuh, Jong Hak, Manohar, Abhijeet, Hsu, Hua-Ling Cynthia, Kuo, Tien-Chien, Avila, Victor
• Granted Patent: US 10,095,412 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are provided.

Claims

1. A memory system comprising:

a plurality of memory dies; and

a controller in communication with the plurality of memory dies, wherein the controller is configured to;

determine a programming status of each of the plurality of memory dies; and

dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies.

2. The memory system of claim 1, wherein the controller is configured to determine the programming status of each of the plurality of memory dies by sending a broadcast status command to all of the memory dies and receiving an indication of programming status from each memory die.

3. The memory system of claim 1, wherein the controller is further configured to dynamically adjust the maximum peak current limit by broadcasting a new maximum peak current limit to the plurality of memory dies.

4. The memory system of claim 3, wherein the new maximum peak current limit is contained in an address field.

5. The memory system of claim 1, wherein the controller is further configured to dynamically adjust the maximum peak current limit before issuing a next program sequence.

6. The memory system of claim 1, wherein the controller is further configured to dynamically adjust the maximum peak current limit during an ongoing program sequence.

7. The memory system of claim 1, wherein the controller is further configured to reset the maximum peak current limit.

8. The memory system of claim 1, wherein at least one of the plurality of memory dies comprises a three-dimensional memory.

9. The memory system of claim 1, wherein the memory system is embedded in a host.

10. The memory system of claim 1, wherein the memory system is removably connected to a host.

11. A method for improving write performance in a multi-die memory system, the method comprising:

performing the following in a memory system comprising a plurality of memory dies, wherein the plurality of memory dies is associated with a current budget;

determining which memory die(s) of the plurality of memory dies are active; and

allocating current from the current budget only to the memory die(s) that are active, wherein the memory die(s) that are active are allocated more than their pro rata share of the current budget, thereby increasing performance of those memory die(s).

12. The method of claim 11, wherein the determining is performed by sending out an inquiry to all of the memory dies and receiving an individual response from each memory die.

13. The method of claim 11, wherein at least one of the plurality of memory dies comprises a three-dimensional memory.

14. The method of claim 11, wherein the memory system is embedded in a host.

15. The method of claim 11, wherein the memory system is removably connected to a host.

16. A memory system comprising:

a plurality of memory dies; and

a controller in communication with the plurality of memory dies, wherein the controller is configured to;

monitor the plurality of memory dies to determine how many of the plurality of memory dies are being programmed; and

make on-the-fly adjustments to change programming speeds of the memory dies that are being programmed based on how many of the plurality of memory dies are being programmed.

17. The memory system of claim 16, wherein the controller is configured to make the on-the-fly adjustments by dynamically increasing or decreasing a maximum peak current limit of the plurality of memory dies based on how many of the plurality of memory dies are being programmed.

18. The memory system of claim 16, wherein at least one of the plurality of memory dies comprises a three-dimensional memory.

19. The memory system of claim 16, wherein the memory system is embedded in a host.

20. The memory system of claim 16, wherein the memory system is removably connected to a host.