MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM

• US 20170139627A1
• Filed: 04/12/2016
• Published: 05/18/2017
• Est. Priority Date: 11/13/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Jong-Min
• Granted Patent: US 10,162,544 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 2212/651 Multi-level translation tables
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A memory system may include a memory device comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of pages having a plurality of memory cells coupled to a plurality of word lines, the memory device being suitable for storing read data and write data requested by a host in the plurality of pages, and a controller suitable for grouping the plurality of pages included in the memory blocks, dividing each of the memory blocks into a plurality of sub-memory blocks, programming data corresponding to a write command received from the host into a first memory block of the memory blocks, performing an update program on the data programmed into the first memory block into the memory blocks in response to a write command for the data programmed into the first memory block from the host, and storing a map list for the sub-memory blocks included in the first memory block in accordance with the update program.

Claims

1. A memory system, comprising:

a memory device comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of pages having a plurality of memory cells coupled to a plurality of word lines, the memory device being suitable for storing read data and write data requested by a host in the plurality of pages; and

a controller suitable for grouping the plurality of pages included in the memory blocks, dividing each of the memory blocks into a plurality of sub-memory blocks, programming data corresponding to a write command received from the host into a first memory block of the memory blocks, performing an update program on the data programmed into the first memory block into the memory blocks in response to a write command for the data programmed into the first memory block from the host, and storing a map list for the sub-memory blocks included in the first memory block in accordance with the update program.

2. The memory system of claim 1, wherein the map list comprises:

a plurality of columns, each column corresponding to a respective memory block, and

a plurality of bit regions included in the columns of the memory blocks, each bit region corresponding to the respective sub-memory block of the memory blocks.

3. The memory system of claim 2, wherein the controller stores valid page count (VPC) information about a first sub-memory block of the first memory block in a bit region corresponding to the first sub-memory block and included in a first column of the map list corresponding to the first memory block in accordance with the update program.

4. The memory system of claim 3, wherein the first memory block is a closed memory block all pages of which have been subjected to a data program operation.

5. The memory system of claim 4, wherein the controller stores:

the map list in a memory of the controller;

VPC information stored in bit regions of the map list corresponding to the closed memory block in the memory blocks; and

map information about the closed memory block in the memory blocks.

6. The memory system of claim 5, wherein the controller identifies valid pages included in the sub-memory blocks of the closed memory blocks by comparing the VPC information stored in the map list with the VPC information stored in the memory blocks with respect to the dosed memory block.

7. The memory system of claim 6, wherein if the VPC information is determined to be changed as a result of the comparison, the controller searches for and checks map information about a second sub-memory block which corresponds to a bit region storing the changed VPC information among the bit regions of the map list.

8. The memory system of claim 7, wherein the controller identifies the valid pages included in the second sub-memory block through the search and check of the map information and updates the map information about the second sub-memory block.

9. The memory system of claim 6, wherein if the VPC information is determined not to be changed as a result of the comparison, the controller identifies the valid pages included in the sub-memory blocks based on the VPC information.

10. The memory system of claim 6, wherein the controller generates an empty memory block, open memory block, or free memory block by performing garbage collection (GC) on the closed memory block whose valid page has been identified.

11. An operating method of a memory system comprising:

dividing each of a plurality of memory blocks into a plurality of sub-memory blocks, by grouping a plurality of pages included in each of the plurality of memory blocks of a memory device and having a plurality of memory cells coupled to a plurality of word lines;

receiving a write command for a first memory block of the memory blocks from a host;

programming data corresponding to the write command received from the host into the first memory block;

receiving a write command for the data programmed into the first memory block from the host; and

performing an update program on the data programmed into the first memory block into the memory blocks and storing a map list for the sub-memory blocks included in the first memory block in accordance with the update program.

12. The operating method of claim 11, wherein the map list comprises:

a plurality of columns each corresponding to the respective memory blocks, and

a plurality of bit regions included in the columns of the memory blocks each of which corresponds to the respective sub-memory blocks of the memory blocks.

13. The operating method of claim 12, wherein the storing of the map list comprises storing valid page count (VPC) information about a first sub-memory block of the first memory block in a bit region corresponding to the first sub-memory block and included in a first column of the map list corresponding to the first memory block in accordance with the update program.

14. The operating method of claim 13, wherein the first memory block comprises closed memory blocks comprising all pages on which a data program has been performed.

15. The operating method of claim 14, wherein the storing of the map list comprises:

storing the map list in a memory of the controller, and

storing in the memory blocks VPC information stored in bit regions included in the columns of the map list and corresponding to the closed memory blocks and map information about the closed memory blocks.

16. The operating method of claim 15, further comprising identifying valid pages included in the sub-memory blocks of the closed memory blocks by comparing the VPC information stored in the map list with the VPC information stored in the memory blocks with respect to the closed memory blocks.

17. The operating method of claim 16, wherein if the VPC information is determined to be changed as a result of the comparison, the identifying of the valid page comprises searching for and checking map information about a second sub-memory block which corresponds to a bit region storing the changed VPC information among the bit regions of the map list.

18. The operating method of claim 17, further comprising:

identifying the valid pages included in the second sub-memory block through the search and check of the map information, and

updating the map information about the second sub-memory block.

19. The operating method of claim 16, wherein if the VPC information is determined to be not changed as a result of the comparison, the identifying of the valid pages comprises identifying the valid pages included in the sub-memory blocks based on the VPC information.

20. The operating method of claim 16, further comprising generating an empty memory block, an open memory block, or a free memory block by performing garbage collection (GC) on the closed memory blocks whose valid page has been identified.