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MULTIPLE RANK HIGH BANDWIDTH MEMORY

  • US 20170140809A1
  • Filed: 11/14/2016
  • Published: 05/18/2017
  • Est. Priority Date: 11/12/2015
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • memory to store data, wherein the memory is to comprise a plurality of memory blocks,wherein an interface is to couple a processor and the plurality of memory blocks through N/2 channels and at least two memory ranks instead of through N channels and one memory rank.

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