MULTIPLE RANK HIGH BANDWIDTH MEMORY

• US 20170140809A1
• Filed: 11/14/2016
• Published: 05/18/2017
• Est. Priority Date: 11/12/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Osborne, Randy B., Mozak, Christopher P., Gutzmann, Michael, McCall, James A.
• Granted Patent: US 9,934,842 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.

Claims

1. An apparatus comprising:

memory to store data, wherein the memory is to comprise a plurality of memory blocks,

wherein an interface is to couple a processor and the plurality of memory blocks through N/2 channels and at least two memory ranks instead of through N channels and one memory rank.

2. The apparatus of claim 1, wherein the interface through the N/2 channels and the at least two memory ranks is to couple the processor and the plurality of memory blocks through about half of a number of wires to be used for the N channels and the one memory rank.

3. The apparatus of claim 1, wherein the processor is to transmit a no operation signal to a non-target rank and a valid command to a target rank.

4. The apparatus of claim 1, wherein a clock signal is to be shared across the at least two ranks.

5. The apparatus of claim 1, wherein a clock enable signal is to be shared across the at least two memory ranks.

6. The apparatus of claim 1, wherein the data is to comprise one or more of:

an input/output data bits, a data bus inversion bit, a data mask bit, a parity bit, or one or more redundant data bits.

7. The apparatus of claim 1, wherein the memory is to support tri-state signaling for a read strobe signal, wherein the read strobe signal is to be shared across the at least two memory ranks.

8. The apparatus of claim 1, wherein a write strobe signal is to be shared across the at least two memory ranks.

9. The apparatus of claim 8, wherein the write strobe signal is to be selectively delayed for each of the at least two memory ranks.

10. The apparatus of claim 1, wherein one or more error signals are to be shared across the at least two memory ranks.

11. The apparatus of claim 10, wherein a trigger point of receiver logic of a memory controller, coupled to the memory, is to be adjusted for a lower supply voltage than a standard supply voltage.

12. The apparatus of claim 1, wherein the memory is to comprise high bandwidth memory having a bandwidth of about 250 GB/s or more.

13. The apparatus of claim 1, wherein the memory is to comprise dynamic random access memory.

14. The apparatus of claim 1, wherein the plurality of memory blocks are to be accessed as an array, wherein the array is to comprise at least two rows and at least two columns.

15. The apparatus of claim 1, further comprising one or more logic components to transmit or receive the data.

16. The apparatus of claim 1, wherein the processor is to comprise one or more processor cores.

17. A computing system comprising:

a processor having one or more processor cores to execute one or more operations on data; and

memory, coupled to the processor, to store the data, wherein the memory is to comprise a plurality of memory blocks,

wherein an interface is to couple the processor and the plurality of memory blocks through N/2 channels and at least two memory ranks instead of through N channels and one memory rank.

18. The system of claim 17, wherein the interface through the N/2 channels and the at least two memory ranks is to couple the processor and the plurality of memory blocks through about half of a number of wires to be used for the N channels and the one memory rank.

19. The system of claim 17, wherein a clock signal is to be shared across the at least two memory ranks.

20. The system of claim 17, wherein a clock enable signal is to be shared across the at least two memory ranks.

21. The system of claim 17, wherein the data is to comprise one or more of:

an input/output data bits, a data bus inversion bit, a data mask bit, a parity bit, or one or more redundant data bits.

22. The system of claim 17, wherein the memory is to support tri-state signaling for a read strobe signal, wherein the read strobe signal is to be shared across the at least two memory ranks.

23. A semiconductor package comprising:

a processor having one or more processor cores; and

memory to store the data, wherein the memory is to comprise a plurality of dynamic random access memory (DRAM) chips,

wherein an interface is to couple the processor and the plurality of DRAM chips through N/2 channels and at least two memory ranks instead of through N Channels and one memory rank.

24. The package of claim 23, wherein the interface through the N/2 channels and the at least two memory ranks is to couple the processor and the plurality of DRAM chips through about half of a number of wires to be used for the N channels and the one memory rank.

25. The package of claim 23, wherein a clock signal or a clock enable signal are to be shared across the at least two memory ranks.