State Dependent Sensing For Wordline Interference Correction

• US 20170140814A1
• Filed: 11/17/2016
• Published: 05/18/2017
• Est. Priority Date: 11/17/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Dutta, Deepanshu, Puthenthermadam, Sarath
• Granted Patent: US 9,721,652 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A variable compensation pass bias based on a state being sensed in non-volatile memory based is provided. Shifts in the apparent charge stored by a memory cell can occur because of coupling based on charge stored by adjacent cells. To account for the shift, compensations can be applied to an adjacent word line when reading based on the different possible conditions of an adjacent cell. The effects of coupling may be more pronounced for memory cells in lower states corresponding to lower threshold voltages. A compensation pass bias can be reduced as the state being sensed at a selected word line increases to account for the different effects. A compensation pass bias for an adjacent word line may be reduced with the application of larger read reference voltages to a selected word line. Other variations to a compensation pass bias are provided.

Claims

1. An apparatus, comprising:

a plurality of memory cells; and

a sense circuit configured to determine a condition of a first unselected memory cell adjacent to a selected memory cell prior to sensing for the selected memory cell;

a read circuit configured to perform for the selected memory cell a plurality of sense operations for a plurality of states, the plurality of sense operations for a particular state of the selected memory cell corresponding to different conditions of the first unselected memory cell; and

a compensation circuit configured to adjust a pass bias applied to the first unselected memory cell during each of the plurality of sense operations, the pass bias including a first pass voltage for a first condition of the first unselected memory cell during sensing for a first state and a second pass voltage for the first condition during sensing for a second state that is different from the first state, the first pass voltage is greater than the second pass voltage.

2. The apparatus of claim 1, wherein:

the read circuit is configured to sense the selected memory cell using a first reference voltage during a first sense operation and a second sense operation for the first state;

the read circuit is configured to sense the selected memory cell using a second reference voltage during a third sense operation and a fourth sense operation for the second state, the second reference voltage is greater than the first reference voltage; and

the compensation circuit is configured to drive the first unselected memory cell with the first pass voltage for the first sense operation, a third pass voltage for the second sense operation, and the second pass voltage for the third sense operation;

the third pass voltage is less than the second pass voltage and the first pass voltage.

3. The apparatus of claim 2, wherein:

the compensation circuit is configured to drive the first unselected memory cell with the first pass voltage while driving the selected memory cell with the first reference voltage and to drive the first unselected memory cell with the third pass voltage while driving the selected memory cell with the first reference voltage; and

the compensation circuit is configured to drive the first unselected memory cell with the second pass voltage while driving the selected memory cell with the second reference voltage.

4. The apparatus of claim 3, wherein:

the compensation circuit is configured to drive the first unselected memory cell with the third pass voltage for the fourth sense operation while driving the selected memory cell with the second reference voltage.

5. The apparatus of claim 3, wherein:

the compensation circuit is configured to drive the first unselected memory cell with a fourth pass voltage for the fourth sense operation while driving the selected memory cell with the second reference voltage, the fourth pass voltage is higher than the third pass voltage and lower than the second pass voltage.

6. The apparatus of claim 2, wherein:

the sense circuit is configured to drive a set of unselected word lines not including the first unselected word line with a single pass voltage while sequentially applying the first pass voltage and the third pass voltage to the first unselected word line, the single pass voltage is less than the first pass voltage and the second pass voltage and is greater than the third pass voltage.

7. The apparatus of claim 2, wherein:

the sense circuit is configured to store a result of the first sense operation and the third sense operation when the first unselected memory cell is in a first condition; and

the sense circuit is configured to store a result of the second sense operation and the fourth sense operation when the first unselected memory cell is in a second condition, the first condition is associated with higher threshold voltages of the first unselected memory cell than the second condition.

8. The apparatus of claim 1, further comprising:

a plurality of NAND strings including the plurality of memory cells, the plurality of NAND strings are arranged in a three-dimensional structure;

a plurality of bit lines coupled to the plurality of NAND strings; and

a source line coupled to the plurality of NAND strings;

wherein the first unselected word line is adjacent to the select word line on a drain side of the selected word line and is programmed subsequent to the selected word line during programming.

9. An apparatus, comprising:

a plurality of memory cells;

a read circuit coupled to the plurality of memory cells, the read circuit reads a selected memory cell by using a first reference voltage for a first state and a second reference voltage for a second state, the first reference voltage is lower than the second reference voltage; and

a compensation circuit coupled to the plurality of memory cells, the compensation circuit sequentially applies to a first unselected memory cell adjacent to the selected memory cell a first set of pass voltages for a plurality of sense operations for the first state and a second set of pass voltages for a plurality of sense operations for the second state, the first set of pass voltages includes a first pass voltage that is higher than each pass voltage of the second set.

10. The apparatus of claim 9, wherein:

the first set of pass voltages includes a first pass voltage and a second pass voltage, the first pass voltage is higher than the second pass voltage;

the second set of pass voltages includes a third pass voltage, the third pass voltage is lower than the first pass voltage and higher than the second pass voltage;

the compensation circuit is configured to apply to the first unselected memory cell the first pass voltage for a first sense operation for the first state and the second pass voltage for a second sense operation for the first state; and

the compensation circuit is configured to apply to the first unselected memory cell the third pass voltage for a third sense operation for the second state.

11. The apparatus of claim 10, wherein:

the second set of pass voltages includes the second pass voltage; and

the compensation circuit is configured to apply the second pass voltage for a fourth sense operation for the second state.

12. The apparatus of claim 10, wherein:

the second set of pass voltages includes a fourth pass voltage; and

the compensation circuit is configured to apply the fourth pass voltage for a fourth sense operation for the second state.

13. The apparatus of claim 10, wherein:

the read circuit is configured to respond to a request to read from the selected memory cell by reading from the first unselected memory cell;

the read circuit is configured to determine data for the selected memory cell based on the first sense operation and the third sense operation if the first unselected memory cell is in a first condition; and

the read circuit is configured to determine data for the selected memory cell based on the second sense operation and the fourth sense operation if the first unselected memory cell is in a second condition.

14. The apparatus of claim 13, further comprising a set of data latches coupled to the first unselected memory cell and the selected memory cell, wherein:

after reading from the first unselected memory cell, the set of data latches store first data if the first unselected memory cell is in the first condition and second data if the first unselected memory cell is in the second condition;

the read circuit is configured to store a result of the first sense operation in the set of data latches if set of data latches stores the first data; and

the read circuit is configured to store a result of the second sense operation if the set of data latches stores the second data.

15. A method, comprising:

sensing a selected word line coupled to a plurality of memory cells for a plurality of states;

sequentially applying a high pass bias and a low pass bias to an adjacent word line for sensing a first state based on direct look ahead values associated with adjacent memory cells of the adjacent word line; and

reducing the high pass bias for sensing each subsequent state that has higher threshold voltages than the first state.

16. The method of claim 15, wherein:

driving a first pass voltage during a first sense operation using a first reference voltage;

driving a second pass voltage during a second sense operation using the first reference voltage, the first pass voltage is greater than the second pass voltage;

driving a third pass voltage during a third sense operation using a second reference voltage, the second reference voltage is higher than the first reference voltage; and

driving the second pass voltage during a fourth sense operation using the second reference voltage, the third pass voltage is greater than the second pass voltage and less than the first pass voltage.

17. The method of claim 16, further comprising:

prior to performing the first sense operation and the second sense operation, reading the adjacent memory cells;

if an adjacent memory cell is in a first set of states, storing a result of the first sense operation in a set of user data latches and discarding a result of the second sense operation for a selected memory cell; and

if the adjacent memory cell is in a second set of states, storing the result of the second sense operation in the set of user data latches and discarding the result of the first sense operation.

18. The method of claim 15, further comprising:

applying to a plurality of unselected word lines not including the adjacent word line one or more different pass biases while applying the high pass bias and the low pass bias.

19. The method of claim 15, wherein:

the selected word line and the adjacent word line are coupled to a NAND string;

the NAND string is coupled to a bit line and a source line;

the unselected word line is adjacent to the selected word line on a drain side; and

the adjacent word line is programmed subsequent to the selected word line.

20. An apparatus, comprising:

a plurality of memory cells;

means for determining a condition of a first unselected memory cell adjacent to a selected memory cell prior to sensing the selected memory cell;

means for reading the selected memory cell using a plurality of sense operations for a plurality of states, the plurality of sense operations for a particular state of the selected memory cell corresponding to different conditions of the first unselected memory cell; and

means for adjusting a pass voltage applied to the first unselected memory cell during each of the plurality of sense operations, a first pass voltage for a first condition of the first unselected memory cell during sensing for a first state is greater than a second pass voltage for the first condition during sensing for a second state that is associated with higher threshold voltages than the first state.