METHOD OF REVERSE TONE PATTERNING

• US 20170140921A1
• Filed: 10/28/2016
• Published: 05/18/2017
• Est. Priority Date: 11/13/2015
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Khusnatdinov, Niyaz, LaBrake, Dwayne L.
• Granted Patent: US 10,211,051 B2
• Time in Patent Office: Days
• CPC Class Codes: B81C 1/00611 Processes for the planarisation of structures planarising depositions C23C, H01L
• CPC Class Codes: B81C 2201/0118 Processes for the planarization of structures
• CPC Class Codes: B81C 2201/0121 involving addition of material followed by removal of parts of said material, i.e. subtractive planarization
• CPC Class Codes: B81C 2201/0126 Processes for the planarization of structures not provided for in B81C2201/0119 - B81C2201/0125
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation

Abstract

Methods of reversing the tone of a pattern having non-uniformly sized features. The methods include depositing a highly conformal hard mask layer over the patterned layer with a non-planar protective coating and etch schemes for minimizing critical dimension variations.

Claims

1. A method comprising:

forming a patterned layer on a substrate, the patterned layer defining a relief pattern having non-uniformly sized features;

depositing a conformal hard mask layer by low temperature deposition over the patterned layer features;

applying a non-planar protective layer over the conformal layer, the protective layer having a planarity efficiency PE of less than 95% (PE 95%) and wherein the protective layer has an etch selectivity ξ

1 relative to the conformal layer of at least 5 (ξ

1≧

5) under first etch conditions and wherein the conformal layer has an etch selectivity ξ

2 relative to the protective layer of greater than 1 (ξ

2>

1) under second etch conditions and wherein the patterned layer has an etch selectivity ξ

3 relative to the conformal layer of at least 5 (ξ

3≧

5) under third etch conditions;

selectively etching the protective coating under the first etch conditions to expose the top surface of the conformal layer extending over the tops of the pattern protruded features;

selectively etching the exposed conformal layer under the second etch conditions to expose the pattern features thereunder; and

selectively etching the exposed pattern features under the third etch conditions to expose the substrate and form a pattern that is the reverse of the relief pattern.

2. The method of claim 1 wherein the low temperature deposition is atomic layer deposition (ALD).

3. The method of claim 1 wherein the non-planar protective coating has a planarity efficiency (PE) of at least 50% (50%≦

PE<

95%).

4. The method of claim 1 wherein the etch selectivity ξ

2 is at least 2 (ξ

2) and the non-planar protective coating has a planarity efficiency (PE) of at least 35% (35%≦

PE<

95%).

5. The method of claim 1 wherein the etch selectivity ξ

2 is at least 5 (ξ

2≧

5) and the non-planar protective coating has a planarity efficiency (PE) of at least 20% (20%≦

PE<

95%).

6. The method of claim 1 wherein the etch selectivity ξ

2 is at least 10 (ξ

2≧

10) and the non-planar protective coating has a planarity efficiency (PE) of at least 15% (15%≦

PE<

95%).

7. The method of claim 1 wherein the etch differential ξ

2 is at least 20 (ξ

2≧

20) and the non-planar protective coating has a planarity efficiency (PE) of at least 10% (10%≦

PE<

95%).

8. The method of claim 1 wherein the planarity efficiency is less than 90% or less than 80% or less than 70% or less than 60%.

9. The method of claim 4 wherein the planarity efficiency is less than 90% or less than 80% or less than 70% or less than 60% or less than 50%.

10. The method of claim 5 wherein the planarity efficiency is less than 90% or less than 80% or less than 70% or less than 60% or less than 50% or less than 40%.

11. The method of claim 6 wherein the planarity efficiency is less than 90% or less than 80% or less than 70% or less than 60% or less than 50% or less than 40% or less than 30%.

12. The method of claim 1 wherein etch selectivities ξ

1 and ξ

3 are maximized so as to obtain reverse tone features with minimized critical dimension variability.

13. The method of claim 1 wherein the conformal layer has a thickness h_HM greater than one-half the space s between the closest features (h_HM≧

s/2).

14. The method of claim 1 wherein the patterned layer is formed by an imprint lithography process.

15. The method of claim 1 wherein the conformal hard mask layer is SiO₂ or Al₂O₃.

16. The method of claim 1 wherein the non-planar protective layer is spin-on carbon (SOC).

17. The method of claim 1 wherein the pattern comprises clusters of nanometer scaled features separated by micron-sized open areas.

18. The method of claim 1 further comprising the step of selectively etching the exposed substrate to transfer the reverse tone pattern into the substrate.

19. A method of manufacturing an article comprising:

forming a pattern on a substrate according to the method of claim 1;

transferring the formed pattern into the substrate; and

processing the substrate to manufacture the article.

20. The method of claim 19 wherein the article is a semiconductor device.