SELF-ALIGNED METAL CUT AND VIA FOR BACK-END-OF-LINE (BEOL) PROCESSES FOR SEMICONDUCTOR INTEGRATED CIRCUIT (IC) FABRICATION, AND RELATED PROCESSES AND DEVICES

• US 20170140986A1
• Filed: 11/12/2015
• Published: 05/18/2017
• Est. Priority Date: 11/12/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Nowak, Matthew Michael, Machkaoutsan, Vladimir, Song, Stanley Seungchul, Zhu, John Jianhong, Bao, Junjing, Xu, Jeffrey Junhao, Badaroglu, Mustafa, Yeap, Choh Fei
• Granted Patent: US 9,793,164 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/461 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/53228 the principal metal being copper

Abstract

Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices, is disclosed. In this manner, mask placement overlay requirements can be relaxed. This relaxation can be multiples of that allowed by conventional BEOL techniques. This is enabled through application of different fill materials for alternating lines in which a conductor will later be placed. With these different fill materials in place, a print cut and via mask is used, with the mask allowed to overlap other adjacent fill lines to that of the desired line. Etching is then applied that is selective to the desired line but not adjacent lines.

Claims

1. A method for providing a metallic interconnection layer of a semiconductor die, comprising:

patterning and filling, using a two-dimension-capable multi-patterning process, alternating first and second sets of lines, the first set of lines and the second set of lines having first and second materials, respectively, the first and second materials having different etch characteristics;

patterning first self-aligned cuts for the first set of lines, the first self-aligned cuts having an overlay margin permitting the first self-aligned cuts to overlap one or more neighboring lines of the second set of lines;

selectively etching, due to the first and second materials having different etch characteristics, the first and second sets of lines and the first self-aligned cuts to remove the first set of lines other than portions of the first set of lines protected by the first self-aligned cuts but not the second set of lines and to provide first trenches at the first set of lines other than the portions of the first set of lines protected by the first self-aligned cuts;

filling the first trenches with a third material having different etch characteristics than the second material;

patterning second self-aligned cuts for the second set of lines, the second self-aligned cuts having an overlay margin permitting the second self-aligned cuts to overlap one or more neighboring trenches of the first trenches;

selectively etching, due to the second and third materials having different etch characteristics, the second set of lines, the first trenches, and the second self-aligned cuts to remove the second set of lines other than portions of the second set of lines protected by the second self-aligned cuts but not the first trenches and to provide second trenches at the second set of lines other than the portions of the second set of lines protected by the second self-aligned cuts;

filling the second trenches with a fourth material having different etch characteristics than the third material;

patterning first self-aligned vias for the first or second trenches with a relaxed overlay margin, the relaxed overlay margin permitting the first self-aligned vias to overlap one or more neighboring trenches of the first or second trenches;

selectively etching, due to the first and second trenches having the third and fourth materials having different etch characteristics, to provide first via holes;

stripping fill materials in the first and second trenches to provide a stripped pattern; and

forming conductive lines and vias in the stripped pattern to provide the metallic interconnection layer for the semiconductor die.

2. The method of claim 1, wherein the two-dimension-capable multi-patterning process is a Lithography Etch Lithography Etch (LELE) process.

3. The method of claim 1, wherein patterning and filling the alternating first and second sets of lines of the first and second materials having different etch characteristics comprises:

patterning a first hard mask stack to provide a first set of line stores;

filling the first set of line stores with the first material of the first and second materials having different etch characteristics;

patterning a second hard mask stack to provide a second set of line stores alternating with the first set of line stores; and

filling the second set of line stores with the second material of the first and second materials having different etch characteristics.

4. The method of claim 1, wherein the first set of lines has a different height or width than the second set of lines, the first set of lines and the second set of lines alternating one with another.

5. The method of claim 1, further comprising, after filling the second trenches and prior to patterning the first self-aligned vias, planarizing the semiconductor die to expose a cut pattern of the first and second trenches.

6. The method of claim 1, wherein selectively etching the first and second sets of lines and the first self-aligned cuts is performed in two etching steps, each of the two etching steps having different etchants.

7. The method of claim 1, wherein selectively etching the second set of lines, the first trenches, and the second self-aligned cuts is performed in two etching steps, each of the two etching steps having different etchants.

8. The method of claim 1, wherein forming the conductive lines and vias in the stripped pattern includes metallization of the stripped pattern with copper.

9. The method of claim 1, further comprising:

patterning second self-aligned vias for the first or second trenches with a second relaxed overlay margin, the second relaxed overlay margin permitting the second self-aligned vias to overlap one or more neighboring trenches of the first or second trenches;

selectively etching, due to the first and second trenches having the third and fourth materials having different etch characteristics, to provide second via holes; and

forming the conductive lines and vias at the second via holes.

10. The method of claim 1, wherein a pitch of the alternating first and second sets of lines is about 24 nanometers.

11. The method of claim 1, wherein patterning operations use a scanner operating at about 193 nanometers and following immersion techniques.

12. One or more non-transitory computer-readable storage media having instructions stored thereon that, responsive to execution by one or more computer processors, performs operations comprising:

patterning and filling, using a two-dimension-capable multi-patterning process, alternating first and second sets of lines, the first set of lines and the second set of lines having first and second materials, respectively, the first and second materials having different etch characteristics;

patterning first self-aligned cuts for the first set of lines, the first self-aligned cuts having an overlay margin permitting the first self-aligned cuts to overlap one or more neighboring lines of the second set of lines;

selectively etching, due to the first and second materials having different etch characteristics, the first and second sets of lines and the first self-aligned cuts to remove the first set of lines other than portions of the first set of lines protected by the first self-aligned cuts but not the second set of lines and to provide first trenches at the first set of lines other than the portions of the first set of lines protected by the first self-aligned cuts;

filling the first trenches with a third material having different etch characteristics than the second material;

patterning second self-aligned cuts for the second set of lines, the second self-aligned cuts having an overlay margin permitting the second self-aligned cuts to overlap one or more neighboring trenches of the first trenches;

selectively etching, due to the second and third materials having different etch characteristics, the second set of lines, the first trenches, and the second self-aligned cuts to remove the second set of lines other than portions of the second set of lines protected by the second self-aligned cuts but not the first trenches and to provide second trenches at the second set of lines other than the portions of the second set of lines protected by the second self-aligned cuts;

filling the second trenches with a fourth material having different etch characteristics than the third material;

patterning first self-aligned vias for the first or second trenches with a relaxed overlay margin, the relaxed overlay margin permitting the first self- aligned vias to overlap one or more neighboring trenches of the first or second trenches;

selectively etching, due to the first and second trenches having the third and fourth materials having different etch characteristics, to provide first via holes;

stripping fill materials in the first and second trenches to provide a stripped pattern; and

forming conductive lines and vias in the stripped pattern to provide a metallic interconnection layer for a semiconductor die.

13. The one or more non-transitory computer-readable storage media of claim 12, wherein patterning and filling the alternating first and second sets of lines of the first and second materials having different etch characteristics comprises:

patterning a first hard mask stack to provide a first set of line stores;

filling the first set of line stores with the first material of the first and second materials having different etch characteristics;

patterning a second hard mask stack to provide a second set of line stores alternating with the first set of line stores; and

filling the second set of line stores with the second material of the first and second materials having different etch characteristics.

14. The one or more non-transitory computer-readable storage media of claim 12, the operations further comprising:

patterning second self-aligned vias for the first or second trenches with a second relaxed overlay margin, the second relaxed overlay margin permitting the second self-aligned vias to overlap one or more neighboring trenches of the first or second trenches;

selectively etching, due to the first and second trenches having the third and fourth materials having different etch characteristics, to provide second via holes; and

forming the conductive lines and vias at the second via holes.

15. The one or more non-transitory computer-readable storage media of claim 12, wherein the first set of lines has a different height or width than the second set of lines, the first set of lines and the second set of lines alternating one with another.

16. The one or more non-transitory computer-readable storage media of claim 12, wherein the operations further comprise, after filling the second trenches and prior to patterning the first self-aligned vias, planarizing the semiconductor die to expose a cut pattern of the first and second trenches.

17. The one or more non-transitory computer-readable storage media of claim 12, wherein selectively etching the first and second sets of lines and the first self-aligned cuts is performed in two etching steps, each of the two etching steps having different etchants.

18. The one or more non-transitory computer-readable storage media of claim 12, wherein selectively etching the second set of lines, the first trenches, and the second self-aligned cuts is performed in two etching steps, each of the two etching steps having different etchants

19. The one or more non-transitory computer-readable storage media of claim 12, wherein forming the conductive lines and vias in the stripped pattern includes metallization of the stripped pattern with copper.

20. An electronic device for integrated circuit (IC) fabrication, comprising:

means for placing a mask;

means for scanning; and

means for managing, wherein the means for managing is capable of;

controlling the means for placing the mask, the means for placing the mask having a maximum placement-accuracy value at which the means for placing the mask is capable of placing a photolithography mask;

controlling the means for scanning, the means for scanning having a maximum scanner-accuracy value at which the means for scanning is capable of patterning a resist through holes or transparencies in the photolithography mask; and

forming, using the means for placing the mask and the means for scanning, metal cuts or vias using the holes or transparencies in the photolithography mask where the holes or transparencies have an overlay margin that is half or more of a pitch of lines from which the metal cuts or vias will later be formed and that is larger than a sum of the maximum placement-accuracy value and the maximum scanner-accuracy value.

21. The electronic device of claim 20, wherein the lines are alternating, each of the lines having a neighboring line with a material having a different etch characteristic.

22. The electronic device of claim 20, wherein the means for managing is further capable of forming the metal cuts or vias by selectively etching a cut or via to a line of the lines rather than a neighboring line of the lines, the line and the neighboring line having different etch characteristics.

23. The electronic device of claim 20, wherein the vias are a smooth column or rectangular cuboid when metalized, the smooth column or rectangular cuboid not having a chamfered surface.

24. The electronic device of claim 20, wherein the means for managing is further capable of forming the lines from which the metal cuts or vias will later be formed.

25. The electronic device of claim 24, wherein the means for managing is further capable of forming the lines using a two-dimension-capable multi-patterning process.

26. The electronic device of claim 25, wherein the two-dimension-capable multi-patterning process is a Lithography Etch Lithography Etch (LELE) process.

27. The electronic device of claim 24, wherein the means for managing is further capable of forming the lines using a Self-Aligned Doubled Patterning (SADP) process.

28. The electronic device of claim 24, wherein the means for managing is further capable of forming the lines using a Self-Aligned Quadruple Patterning (SAQP) process.

29. The electronic device of claim 20, wherein the sum of the maximum placement-accuracy value and the maximum scanner-accuracy value is about 15 nanometers, the pitch of the lines is about 24 nanometers, and the overlay margin is greater than 15 nanometers.

30. The electronic device of claim 20, wherein the maximum scanner-accuracy value is a fundamental limitation of a 193 nanometer laser.