FIN FIELD EFFECT TRANSISTOR, SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

• US 20170141106A1
• Filed: 11/16/2015
• Published: 05/18/2017
• Est. Priority Date: 11/16/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tseng, Horng-Huei, Lin, Chih-Han, Chang, Che-Cheng
• Granted Patent: US 10,020,304 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate
• CPC Class Codes: H01L 29/7855 : with at least two independent gates

Abstract

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

Claims

1. A method for fabricating a fin field effect transistor (FinFET), comprising:

patterning a substrate to form a plurality of trenches in the substrate and a semiconductor fin between the trenches;

forming a plurality of insulators in the trenches;

forming a first dielectric layer to cover the semiconductor fin and the insulators;

forming a dummy gate strip on the first dielectric layer, a lengthwise direction of the dummy gate strip being different from a lengthwise direction of the semiconductor fin;

forming a pair of spacers on sidewalls of the dummy gate strip;

removing the dummy gate strip and the first dielectric layer underneath until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed;

forming a second dielectric layer to selectively cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer; and

forming a gate between the spacers to cover the second dielectric layer, the exposed sidewalls of the spacers and the exposed portions of the insulators.

2. The method of claim 1, wherein the spacers are formed on the first dielectric layer and extend along the sidewalls of the dummy gate strip before the dummy gate strip is removed.

3. The method of claim 1, wherein the dummy gate strip and the first dielectric layer are removed to form a cavity between the spacers and the second dielectric layer are formed on the portion of the semiconductor fin exposed by the cavity.

4. The method of claim 3, wherein the dummy gate strip, the first dielectric layer and portions of the insulators are removed by an etch process during the formation of the cavity.

5. The method of claim 1, wherein the second dielectric layer is formed by thermal oxidation.

6. The method of claim 1, wherein the gate having a width greater than 50 nm is formed between the spacers to cover the second dielectric layer, the exposed sidewalls of the spacers and the exposed portions of the insulators.

7. The method of claim 1 further comprising:

forming a source and a drain over portions of the semiconductor fin before the dummy gate strip is removed.

8. A method for fabricating a semiconductor device, comprising:

patterning a substrate to form a plurality of trenches in the substrate and semiconductor fins between the trenches;

forming a plurality of insulators in the trenches;

forming a first dielectric layer to cover the semiconductor fins and the insulators;

forming at least one first dummy gate strip and at least one second dummy gate strip on the first dielectric layer, wherein lengthwise directions of the first and second dummy gate strips are different from a lengthwise direction of the semiconductor fins, and a width of the first dummy gate strip is smaller than a width of the second dummy gate strip;

forming a pair of first spacers and a pair of second spacers on sidewalls of the first and second dummy gate strips respectively;

removing the first dummy gate strip to form a first cavity,

removing the second dummy gate strip and the first dielectric layer underneath until sidewalls of the second spacers, a portion of the semiconductor fins and portions of the insulators are exposed to form a second cavity;

forming a second dielectric layer in the second cavity to selectively cover the exposed portion of the semiconductor fins, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer;

forming a first gate in the first cavity; and

forming a second gate in the second cavity to cover the second dielectric layer, the exposed sidewalls of the spacers and the exposed portions of the insulators.

9. The method of claim 8, wherein the first and second dummy gate strips are removed in a same process.

10. The method of claim 8, wherein a method of forming the first and second dummy gate strips comprises:

forming a conductive layer on the first dielectric layer; and

patterning the conductive layer to form a first conductive strip having a first width and a second conductive strip having a second width, the first width being smaller than the second width.

11. The method of claim 8, wherein the first spacers are formed on the first dielectric layer and extend along the sidewalls of the first dummy gate strip, and the second spacers are formed on the first dielectric layer and extend along the sidewalls of the second dummy gate strip.

12. The method of claim 8, wherein the second dummy gate strip, the first dielectric layer underneath and portions of the insulators are removed by an etch process during the formation of the second cavity.

13. The method of claim 8, wherein the second dielectric layer is formed by thermal oxidation.

14. The method of claim 8, wherein the first gate having a width between 5 nm to 50 nm is formed in the first cavity and the second gate having a width greater than 50 nm is formed in the second cavity to cover the second dielectric layer, the exposed sidewalls of the spacers and the exposed portions of the insulators.

15. The method of claim 8 further comprising:

forming sources and drains over portions of the semiconductor fins before the first and second dummy gate strips are removed.

16. A semiconductor device, comprising:

a substrate comprising trenches and semiconductor fins between trenches;

a plurality of insulators in the trenches;

a first dielectric layer covering the semiconductor fins and the insulators, the first dielectric layer exposing a portion of the semiconductor fins and portions of the insulators;

a pair of first spacers disposed on the first dielectric layer;

a first gate disposed on the first dielectric layer and between the first spacers;

a pair of second spacers disposed on the first dielectric layer;

a second dielectric layer disposed between the second spacers, wherein the second dielectric layer selectively covers the exposed portion of the semiconductor fins, and a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer; and

a second gate disposed between the second spacers to cover the second dielectric layer, the exposed sidewalls of the spacers and the exposed portions of the insulators, wherein a width of the first gate is smaller than a width of the second gate.

17. The semiconductor device of claim 16, wherein the thickness of the first dielectric layer ranges from 0.2 nm to 5 nm and the thickness of the second dielectric layer ranges from 5 nm to 50 nm.

18. The semiconductor device of claim 16, wherein the width of the first gate ranges from 5 nm to 50 nm and the width of the second gate is greater than 50 nm.

19. The semiconductor device of claim 16, wherein the width of the second gate substantially equals to a gap between the pair of second spacers.

20. The semiconductor device of claim 16, wherein the second dielectric layer is disposed between the exposed portion of the semiconductor fin and the second gate.