Butted Body Contact for SOI Transistor

• US 20170141126A1
• Filed: 03/23/2016
• Published: 05/18/2017
• Est. Priority Date: 11/18/2015
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Willard, Simon Edward
• Granted Patent: US 9,842,858 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/213 in integrated circuits
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence

Abstract

Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Claims

1. A semiconductor structure comprising:

a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type;

a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type;

a first drain region adjacent to the first body region having a second conductivity type;

a first source region adjacent to the first body region having the second conductivity type;

a second source region adjacent to the second body region having the second conductivity type;

a second drain region adjacent to the second body region having the second conductivity type,

the first source region and the second drain region defining a first common source/drain region having the second conductivity type;

a first non-conductive isolation region configured to form an interruption in the second body region to divide the second body region in two separate second body regions;

at least one first body contact region of the first conductivity type formed within the first common source/drain region separate from the first and the second body regions and abutting the first non-conductive isolation region; and

at least one first body tab of the first conductivity type extending across the first common source/drain region in contact with the first body region and the at least one first body contact region,

wherein the first non-conductive isolation region, the at least one first body contact region and the at least one first body tab define a first butted body tie structure.

2. The semiconductor structure of claim 1, wherein the first non-conductive isolation region is further configured to extend a silicon region of the first common source/drain region to provide a region of contiguous silicon for the at least one first body contact region and the at least one first body tab.

3. The semiconductor structure of claim 1 or claim 2, wherein the first non-conductive isolation region is further configured to form an interruption in the second source region to divide said source region in two separate second source regions.

4. The semiconductor structure of claim 1 or claim 2, wherein a length of the at least one first body tab is greater than a length defined by a spacing between the first body region and the second body region.

5. The semiconductor structure of claim 1, wherein the first body tab extends in a direction perpendicular to a direction defined by the first and the second body regions along the width of the body regions.

6. The semiconductor structure of claim 1, further comprising:

at least one second body contact region of the first conductivity type separate from the first and the second body regions; and

at least one second body tab of the first conductivity type extending into the second source region and in contact with one of the two separate second body regions and the at least one second body contact.

7. The semiconductor structure of claim 6, further comprising:

an additional second body contact region of the first conductivity type separate from the first and the second body regions; and

an additional second body tab of the first conductivity type extending into the second source region and in contact with the other of the two separate second body regions.

8. The semiconductor structure of claim 6 or claim 7, wherein the at least one second body contact region is formed within the second source region such as to be laterally surrounded by the second source region.

9. The semiconductor structure of claim 6 or claim 7, wherein the at least one second body contact region abuts the second source region.

10. The semiconductor structure of claim 9, wherein the at least one second body contact region and the additional second body contact region form a contiguous silicon region.

11. The semiconductor structure of any one of claim 1, 2 or 6, wherein the first and the second gate polysilicon structures respectively define fingers of a first and a second transistor arranged in a cascode configuration.

12. The semiconductor structure of claim 11, further comprising:

an additional first finger of the first transistor;

an additional second finger of the second transistor; and

an additional first butted body tie structure comprising;

i) an additional first body contact region;

ii) an additional first body tab; and

iii) the first non-conductive isolation region,

wherein the additional first finger, the additional second finger and the additional first butted body tie structure are mirrored with respect to the first finger, the second finger and the first butted body tie structure, around a centerline of the semiconductor structure defined by a center region of the second source region along a width of the second source region, the second source region being a common source region to the second finger and the additional second finger.

13. The semiconductor structure of claim 1, further comprising:

a third gate polysilicon structure defining a third body region of the first conductivity type;

a third drain region adjacent to the third body region having the second conductivity type, the third drain region and the second source region defining a second common drain/source region having the second conductivity type; and

a third source region adjacent to the third body region having the second conductivity type;

wherein the first non-conductive isolation region is further configured to form an interruption in the third body region and in the second common source/drain region to respectively divide the third body region and the second common source/drain region in two separate third body regions and two separate second common source/drain regions.

14. The semiconductor structure of claim 13, further comprising a second butted body tie configuration, the second butted body tie configuration comprising:

a second non-conductive isolation region configured to form an interruption in one of the two separate third body regions;

a second body contact region of the first conductivity type formed within a region of the second common source/drain region separate from the second and the third body regions and abutting the second non-conductive isolation region; and

a second body tab of the first conductivity type extending across a region of the second common source/drain region in contact with one of the two separate second body region and the second body contact region,

wherein the region of the second common source/drain region is one of the two separate second common source/drain regions adjacent to the one of the two separate second body regions.

15. The semiconductor structure of claim 14, wherein the second non-conductive isolation region is further configured to extend a silicon region of the second common source/drain region to provide a region of contiguous silicon for the second body contact region and the second body tab.

16. The semiconductor structure of claim 14 or claim 15, wherein the second non-conductive isolation region is further configured to form an interruption in the third source region to divide said source region in two separate third source regions.

17. The semiconductor structure of claim 14 or claim 15, wherein a length of the at least one second body tab is greater than a length defined by a spacing between the second body region and the third body region.

18. The semiconductor structure of claim 14, wherein the second body tab extends in a direction perpendicular to a direction defined by the second and the third body regions.

19. The semiconductor structure of claim 14, further comprising an additional second butted body tie configuration associated to the other of the two separate second body regions.

20. The semiconductor structure of claim 19, wherein the additional second butted body tie comprises:

an additional second non-conductive isolation region configured to form an interruption in the other of the two separate third body regions;

an additional second body contact region of the first conductivity type formed within a region of the second common source/drain region separate from the second and the third body regions and abutting the additional second non-conductive isolation region; and

an additional second body tab of the first conductivity type extending across a region of the second common source/drain region in contact with the other of the two separate second body regions and the additional second body contact region,

wherein the region of the second common source/drain region is one of the two separate second common source/drain regions adjacent to the other of the two separate second body regions.

21. The semiconductor structure of claim 20, wherein the additional second non-conductive isolation region is further configured to extend a silicon region of the second common source/drain region to provide a region of continuous silicon for the additional second body contact region and the additional second body tab.

22. The semiconductor structure of claim 20 or claim 21, wherein the additional second non-conductive isolation region is further configured to form an interruption in the third source region to further divide said source region in further separate source regions.

23. The semiconductor structure of claim 20 or claim 21, wherein a length of the additional second body tab is greater than a length defined by a spacing between the second body region and the third body region.

24. The semiconductor structure of claim 20, wherein the additional second body tab extends in a direction perpendicular to a direction defined by the second and the third body regions.

25. The semiconductor structure of claim 19, further comprising at least one third butted body tie structure associated to one of the separate third body regions, the at least one third butted body tie structure comprising:

a third body contact region of the first conductivity type separate from the second and third body regions; and

a third body tab of the first conductivity type extending across the third source region and in contact with one of the separate third body regions and the third body contact region.

26. The semiconductor structure of claim 25, further comprising a plurality of third butted body tie structures each associated to a different third body region of the separate third body regions.

27. The semiconductor structure of claim 25 or claim 26, wherein the third body contact region is formed within the third source region such as to be laterally surrounded by the third source region.

28. The semiconductor structure of claim 26, wherein at least one third body contact region of the plurality of third butted body tie structures abuts the third source region.

29. The semiconductor structure of claim 28, wherein two or more third body contact regions of the plurality of third butted body tie structures form a contiguous silicon region.

30. The semiconductor structure of any one of claims 14, 19, 25 and 26, wherein the first, the second and the third gate polysilicon structures respectively define fingers of a first, a second and a third transistor arranged in a cascode configuration.

31. The semiconductor structure of claim 30, further comprising:

an additional first finger of the first transistor;

an additional second finger of the second transistor;

an additional third finger of the third transistor;

at least one additional first butted body tie structure comprising;

i) an additional first body contact region;

ii) an additional first body tab; and

iii) the first non-conductive isolation region; and

at least one additional second butted body tie structure comprising;

iv) an additional second body contact region;

v) an additional second body tab; and

vi) the second non-conductive isolation region;

wherein the additional first finger, the additional second finger, the additional third finger, the additional first butted body tie structure and the additional second butted body tie structure are mirrored with respect to the first finger, the second finger, the third finger, the first butted body tie structure and the second butted body tie structure, around a centerline of the semiconductor structure defined by a center region of the third source region along a width of the third source region, the third source region being a common source region to the third finger and the additional third finger.

32. A semiconductor structure comprising:

at least two instantiations of the semiconductor structure according to claim 12 mirrored around a centerline of the first drain regions of the first fingers of the at least two instantiations, the centerline being along a width of the first drain regions defining a common first drain region, the semiconductor structure further comprising;

a first perpendicular polysilicon structure joining the first gate polysilicon structures of the at least two instantiations at a first end of the first gate polysilicon structures, the first perpendicular polysilicon structure defining an underlying common body region to the first body regions of the at least two instantiations; and

a first horizontal polysilicon structure extending from a midpoint of the first perpendicular polysilicon structure through a first edge of a silicon region of the semiconductor structure, the first horizontal polysilicon structure extending the underlying common body region to the first edge of the silicon region.

33. The semiconductor structure of claim 32, further comprising:

a second perpendicular polysilicon structure joining the first gate polysilicon structures of the at least two instantiations at a second end of the first gate polysilicon structures, the second perpendicular polysilicon structure defining an underlying common body region to the first body regions of the at least two instantiations; and

a second horizontal polysilicon structure extending from a midpoint of the second perpendicular polysilicon structure through a second edge of the silicon region of the semiconductor structure opposite from the first edge, the second horizontal polysilicon structure extending the underlying common body region to the second edge of the silicon region.

34. A semiconductor structure comprising:

at least two instantiations of the semiconductor structure according to claim 31 mirrored around a centerline of the first drain regions of the first fingers of the at least two instantiations, the centerline being along a width of the first drain regions defining a common first drain region, the semiconductor structure further comprising;

a first perpendicular polysilicon structure joining the first gate polysilicon structures of the at least two instantiations at a first end of the first gate polysilicon structures, the first perpendicular polysilicon structure defining an underlying common body region to the first body regions of the at least two instantiations; and

a first horizontal polysilicon structure extending from a midpoint of the first perpendicular polysilicon structure through a first edge of a silicon region of the semiconductor structure, the first horizontal polysilicon structure extending the underlying common body region to the first edge of the silicon region.

35. The semiconductor structure of claim 34, further comprising:

a second perpendicular polysilicon structure joining the first gate polysilicon structures of the at least two instantiations at a second end of the first gate polysilicon structures, the second perpendicular polysilicon structure defining an underlying common body region to the first body regions of the at least two instantiations; and

a second horizontal polysilicon structure extending from a midpoint of the second perpendicular polysilicon structure through a second edge of the silicon region of the semiconductor structure opposite from the first edge, the second horizontal polysilicon structure extending the underlying common body region to the second edge of the silicon region.

36. The semiconductor structure of claim 11, wherein the transistors of the cascode configuration are metal-oxide-semiconductor field effect transistors (MOSFETs).

37. The semiconductor structure of claim 36, wherein the transistors are fabricated using a technology according to one of:

a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire (SOS) technology.

38. The semiconductor structure of claim 30, wherein the transistors are metal-oxide-semiconductor field effect transistors (MOSFETs).

39. The semiconductor structure of claim 38, wherein the transistors are fabricated using a technology according to one of:

a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire (SOS) technology.

40. The semiconductor structure according to claim 36, adapted for use as an amplifier in an application selected from among a group consisting of:

a) a radio frequency (RF) amplifier, b) an RF power amplifier, c) a cellular RF power amplifier, d) a switching RF power amplifier, e) a CMOS (complementary metal-oxide-semiconductor) RF power amplifier, and f) a cellular CMOS RF power amplifier.

41. The semiconductor structure according to claim 40, wherein a class of operation of the amplifier is one or more of:

i) linear class A, ii) linear class A/B, iii) saturated class B, iv) saturated class C, v) switching class D, vi) switching class E, and vii) switching class F.

42. The semiconductor structure according to claim 38, adapted for use as an amplifier in an application selected from among a group consisting of:

a) a radio frequency (RF) amplifier, b) an RF power amplifier, c) a cellular RF power amplifier, d) a switching RF power amplifier, e) a CMOS (complementary metal-oxide-semiconductor) RF power amplifier, and f) a cellular CMOS RF power amplifier.

43. The semiconductor structure according to claim 42, wherein a class of operation of the amplifier is one or more of:

i) linear class A, ii) linear class A/B, iii) saturated class B, iv) saturated class C, v) switching class D, vi) switching class E, and vii) switching class F.

44. A semiconductor structure comprising a plurality of transistors, the semiconductor structure comprising:

an insulating layer;

a silicon layer overlying the insulating layer;

active regions formed in the silicon layer, the active regions extending through the silicon layer to contact the insulating layer, the active regions comprising body regions, source regions and drain regions of one or more fingers of each transistor of the plurality of transistors configured as a cascode stack arranged from top to bottom, wherein for each two consecutive transistors of the cascode stack, a source region of a finger of a top transistor and the drain region of a finger of a bottom transistor of the each two consecutive transistors are formed in a common source/drain region of the silicon layer; and

at least one butted body tie structure associated to the top finger, comprising;

i) a non-conductive isolation region;

ii) a body contact region formed within the common source/drain region of the fingers of two consecutive transistors separate from the body regions of the fingers and abutting an isolation region of the non-conductive isolation region; and

iii) a body tab region formed in the silicon layer in contact with the body region of the finger of the top transistor and the body contact region,

wherein the at least one non-conductive isolation region is configured to;

form an interruption in a region of the silicon layer which defines the body region of the finger of the bottom transistor to divide said body region in separate body regions, and

extend the interruption in a region of the silicon layer which defines body regions and common source/drain regions of fingers of one or more consecutive transistors adjacent to the bottom transistor to divide said regions in separate regions.

45. The semiconductor structure of claim 44, further comprising:

additional butted body tie structures associated to the bottom finger, wherein the body tab region of each of the additional butted body tie structures is in contact with a separate body region of the finger of the bottom transistor.

46. The semiconductor structure of claim 45, wherein:

each finger of a transistor of the plurality of transistors comprises a number of associated butted body tie structures equal to a number of separate body regions of the each finger, and

the body tab region of each of the associated butted body tie structures is in contact with a separate body region of the each finger.

47. The semiconductor structure of claim 44 or claim 45, wherein:

the cascode stack comprises a first top transistor and a last bottom transistor,

each transistor of the plurality of transistors of the cascode stack comprises two or more fingers; and

regions of any two fingers of the each transistor are mirrored around a centerline defined by a center region of a common source region along a width of the common source region, the common source region being the source region of two fingers of the last bottom transistor.

48. The semiconductor structure of claim 47, wherein the semiconductor structure is symmetric with respect to the centerline.

49. The semiconductor structure of claim 47, wherein each finger of the first top transistor comprises one and only one associated butted body tie structure.

50. The semiconductor structure of claim 47, wherein each finger of a transistor adjacent to the first top transistor comprises one and only one associated butted body tie structure.

51. The semiconductor structure of claim 50, wherein regions of any two fingers of the each transistor are further mirrored around a centerline defined by a center region of a common drain region along a width of the common drain region, the common drain region being the drain region of two fingers of the first top transistor, the two fingers comprising a first top finger and a second top finger, the semiconductor structure further comprising:

a perpendicular polysilicon structure joining gate polysilicon structures of the first and the second top fingers, the perpendicular polysilicon structure defining an underlying common body region to the body regions of the first and the second top fingers; and

a horizontal polysilicon structure extending from a midpoint of the perpendicular polysilicon structure through an edge of a silicon region of the semiconductor structure, the horizontal polysilicon structure extending the underlying common body region to the edge of the silicon region.

52. The semiconductor structure of claim 51, wherein the semiconductor structure is symmetric with respect to a centerline passing through centers of the one or more fingers of each transistor of the plurality of transistors along the length of the one or more fingers.

53. The semiconductor structure of claim 48, wherein the semiconductor structure is symmetric with respect to a centerline passing through centers of the one or more fingers of each transistor of the plurality of transistors along the length of the one or more fingers.

54. The semiconductor structure of claim 49, wherein the semiconductor structure is symmetric with respect to a centerline passing through centers of the one or more fingers of each transistor of the plurality of transistors along the length of the one or more fingers.

55. A method for providing a body tie to transistors arranged in a cascode configuration comprising:

a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type;

a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type;

a first drain region adjacent to the first body region having a second conductivity type;

a first source region adjacent to the first body region having the second conductivity type;

a second source region adjacent to the second body region having the second conductivity type;

a second drain region adjacent to the second body region having the second conductivity type, and

the first source region and the second drain region defining a first common source/drain region having the second conductivity type;

the method comprising;

forming, by way of a first non-conductive isolation region, an interruption in the second body region to divide the second body region in two separate second body regions;

forming at least one first body contact region of the first conductivity type within the first common source/drain region separate from the first and the second body regions and abutting the first non-conductive isolation region; and

forming at least one first body tab of the first conductivity type extending across the first common source/drain region in contact with the first body region and the at least one first body contact region,

wherein the first non-conductive isolation region, the at least one first body contact region and the at least one first body tab define a first butted body tie structure.