SEMICONDUCTOR DEVICE

• US 20170141131A1
• Filed: 01/27/2017
• Published: 05/18/2017
• Est. Priority Date: 03/03/2015
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MIURA, Kentaro, MAEDA, Yuya, NAKANO, Shintaro
• Application Number:
  US15/418,002
• Publication Number:
  US 20170141131A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

According to one embodiment, a semiconductor device includes a substrate, a semiconductor layer, a source electrode, a drain electrode, first insulating portion and second insulating portions. The semiconductor layer includes an oxide and is separated from the substrate in a first direction. The source electrode is electrically connected to the semiconductor layer. The drain electrode is electrically connected to the semiconductor layer and is arranged with the source electrode in a second direction crossing the first direction. The first insulating portion is provided between the substrate and the semiconductor layer. The semiconductor layer is provided between the first and second insulating portions. The first insulating portion includes a first silicon nitride layer, and a first aluminum oxide layer stacked with the first silicon nitride layer. The second insulating portion includes a second aluminum oxide layer, and a second silicon nitride layer stacked with the second aluminum oxide layer.

Claims

1. A semiconductor device, comprising:

a substrate;

a semiconductor layer including an oxide and being separated from the substrate in a first direction;

a source electrode electrically connected to the semiconductor layer;

a drain electrode electrically connected to the semiconductor layer and arranged with the source electrode in a second direction crossing the first direction;

a first insulating portion provided between the substrate and the semiconductor layer; and

a second insulating portion, the semiconductor layer being provided between the first insulating portion and the second insulating portion,

the first insulating portion including a first silicon nitride layer, and a first aluminum oxide layer stacked with the first silicon nitride layer,

the second insulating portion including a second aluminum oxide layer, and a second silicon nitride layer stacked with the second aluminum oxide layer.

2. The device according to claim 1, wherein

the first insulating portion includes a first layer positioned between the first silicon nitride layer and the first aluminum oxide layer, and

the second insulating portion includes a second layer positioned between the second aluminum oxide layer and the second silicon nitride layer.

3. The device according to claim 2, wherein

a proportion of nitrogen of the first layer is larger than a proportion of nitrogen of the second layer,

a proportion of oxygen of the first layer is smaller than a proportion of oxygen of the second layer,

a proportion of aluminum of the first layer is smaller than a proportion of aluminum of the second layer, and

a proportion of silicon of the first layer is larger than a proportion of silicon of the second layer.

4. The device according to claim 2, further comprising a third insulating portion provided on the second insulating portion,

the third insulating portion including:

a first region overlapping the semiconductor layer in the first direction; and

a second region being arranged with the first region in the second direction and not overlapping the semiconductor layer in the first direction,

a portion of the second region not overlapping the first layer and the second layer in the first direction.

5. The device according to claim 4, wherein the portion of the second region includes a trench portion provided around the semiconductor layer.

6. The device according to claim 4, wherein the third insulating portion includes one of silicon oxide or silicon oxynitride.

7. The device according to claim 1, wherein

the first aluminum oxide layer is provided between the first silicon nitride layer and the semiconductor layer, and

the second aluminum oxide layer is provided between the second silicon nitride layer and the semiconductor layer.

8. The device according to claim 1, wherein

a thickness of the first silicon nitride layer is not less than 10 nanometers and not more than 100 nanometers,

a thickness of the first aluminum oxide layer is not less than 5 nanometers and not more than 100 nanometers,

a thickness of the second aluminum oxide layer is not less than 5 nanometers and not more than 100 nanometers, and

a thickness of the second silicon nitride layer is not less than 10 nanometers and not more than 100 nanometers.

9. The device according to claim 1, further comprising a gate electrode,

the first insulating portion being provided between the semiconductor layer and the gate electrode, the semiconductor layer including an oxide of at least one of indium, gallium, or zinc.

10. The device according to claim 1, further comprising a gate electrode,

the second insulating portion being provided between the semiconductor layer and the gate electrode, the semiconductor layer including an oxide of at least one of indium, gallium, or zinc.