SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20170141186A1
• Filed: 06/30/2015
• Published: 05/18/2017
• Est. Priority Date: 06/30/2014
• Status: Active Grant

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Shiomi, Hiromu
• Granted Patent: US 9,954,054 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A fourth impurity region includes a first region facing a bottom portion of a trench and a part of a second impurity region and a second region facing the second impurity region. A first impurity region includes a third region in contact with a side surface of the trench, the second impurity region, the first region, and a second region and a fourth region which is located on a side of a second main surface relative to the third region, electrically connected to the third region, and lower in impurity concentration than the third region. A surface of the first region facing the second main surface is located on the side of the second main surface in a direction perpendicular to the second main surface relative to a surface of the second region facing the second main surface.

Claims

1. A silicon carbide semiconductor device comprising:

a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface,

the silicon carbide substrate including a first impurity region having a first conductivity type, a second impurity region which is in contact with the first impurity region and has a second conductivity type different from the first conductivity type, a third impurity region which has the first conductivity type and is spaced apart from the first impurity region by the second impurity region, and a fourth impurity region which has the second conductivity type and is higher in impurity concentration than the second impurity region,

the first main surface of the silicon carbide substrate having a trench provided, the trench having a side surface continuous to the first main surface and a bottom portion continuous to the side surface,

the fourth impurity region including a first region facing the bottom portion of the trench and a part of the second impurity region and a second region facing the second impurity region,

the first impurity region including a third region in contact with the side surface of the trench, the second impurity region, the first region, and the second region and a fourth region which is located on a side of the second main surface relative to the third region, electrically connected to the third region, and lower in impurity concentration than the third region,

a surface of the first region facing the second main surface being located on the side of the second main surface in a direction perpendicular to the second main surface relative to a surface of the second region facing the second main surface;

a gate insulating film in contact with the third region, the second impurity region, and the third impurity region at the side surface of the trench;

a gate electrode provided on the gate insulating film;

a first electrode electrically connected to the third impurity region on a side of the first main surface; and

a second electrode electrically connected to the fourth region on the side of the second main surface,

the fourth impurity region being electrically connected to the first electrode.

2. The silicon carbide semiconductor device according to claim 1, wherein

the fourth impurity region further includes a fifth region which is located opposite to the second impurity region when viewed from the second region and is in contact with the second region.

3. The silicon carbide semiconductor device according to claim 2, wherein

a side surface of the second region is provided to protrude toward the side surface of the trench relative to a side surface of the fifth region.

4. The silicon carbide semiconductor device according to claim 2, wherein

a side surface of the second region is provided to retract toward a side opposite to the side surface of the trench relative to a side surface of the fifth region.

5. The silicon carbide semiconductor device according claim 1, wherein

a distance between the second impurity region and the first region in a direction perpendicular to the second main surface is not smaller than 0.2 μ

m and not greater than 2 μ

m.

6. The silicon carbide semiconductor device according claim 1, wherein

a distance between a point of contact between the side surface and the bottom portion of the trench and a side surface of the first region in a direction in parallel to the second main surface is not smaller than 0.1 μ

m and not greater than 0.5 μ

m.

7. The silicon carbide semiconductor device according to claim 1, wherein

a distance between a side surface of the first region and a side surface of the second region in a direction in parallel to the second main surface is not smaller than 0.6 μ

m and not greater than 1.5 μ

m.

8. The silicon carbide semiconductor device according to claim 1, wherein

a concentration of an impurity in the third region is not lower than 1×

10¹⁶ cm<sup>−

3</sup> and not higher than 4×

10¹⁷ cm<sup>−

3</sup>.

9. The silicon carbide semiconductor device according to claim 1, wherein

a concentration of an impurity in the second impurity region is not lower than 1×

10¹⁵ cm′ and

not higher than 4×

10¹⁷ cm<sup>−

3</sup>.

10. A method for manufacturing a silicon carbide semiconductor device comprising:

preparing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface,

the silicon carbide substrate including a first impurity region having a first conductivity type, a second impurity region which is in contact with the first impurity region and has a second conductivity type different from the first conductivity type, a third impurity region which has the first conductivity type and is spaced apart from the first impurity region by the second impurity region, and a fourth impurity region which has the second conductivity type and is higher in impurity concentration than the second impurity region,

the first main surface of the silicon carbide substrate having a trench provided, the trench having a side surface continuous to the first main surface and a bottom portion continuous to the side surface,

the fourth impurity region including a first region facing the bottom portion of the trench and a part of the second impurity region and a second region facing the second impurity region,

the first impurity region including a third region in contact with the side surface of the trench, the second impurity region, the first region, and the second region and a fourth region which is located on a side of the second main surface relative to the third region, electrically connected to the third region, and lower in impurity concentration than the third region,

a surface of the first region facing the second main surface being located on the side of the second main surface in a direction perpendicular to the second main surface relative to a surface of the second region facing the second main surface;

forming a gate insulating film in contact with the third region, the second impurity region, and the third impurity region at the side surface of the trench;

forming a gate electrode on the gate insulating film;

forming a first electrode electrically connected to the third impurity region on a side of the first main surface; and

forming a second electrode electrically connected to the fourth region on the side of the second main surface,

the fourth impurity region being electrically connected to the first electrode.

11. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein

forming the silicon carbide substrate includes

forming the fourth region through epitaxial growth,

forming the first region by implanting ions into the fourth region,

forming the third region on the first region through epitaxial growth, and

forming the second region by implanting ions into the third region.

12. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein

forming the silicon carbide substrate further includes forming a sixth region which has the first conductivity type and is higher in impurity concentration than the fourth region by implanting ions into the fourth region, and

in forming the third region, the third region is formed on each of the first region and the sixth region.

13. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein

forming the silicon carbide substrate includes

forming the fourth region through epitaxial growth,

forming the third region on the fourth region through epitaxial growth,

forming the first region in contact with the fourth region by implanting ions into the fourth region with first implantation energy, and

forming the second region in contact with the third region by implanting ions into the third region with second implantation energy lower than the first implantation energy.

14. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein

forming the silicon carbide substrate further includes forming the second impurity region in contact with both of the second region and the third region through epitaxial growth.

15. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein

the fourth impurity region further includes a fifth region which is located opposite to the second impurity region when viewed from the second region and is in contact with the second region.

16. The method for manufacturing a silicon carbide semiconductor device according to claim 15, wherein

a side surface of the second region is provided to protrude toward the side surface of the trench relative to a side surface of the fifth region.

17. The method for manufacturing a silicon carbide semiconductor device according to claim 15, wherein

a side surface of the second region is provided to retract toward a side opposite to the side surface of the trench relative to a side surface of the fifth region.

18. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein

a distance between the second impurity region and the first region in a direction perpendicular to the second main surface is not smaller than 0.2 μ

m and not greater than 2 μ

m.

19. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein

a distance between a point of contact between the side surface and the bottom portion of the trench and a side surface of the first region in a direction in parallel to the second main surface is not smaller than 0.1 μ

m and not greater than 0.5 μ

m.

20. The method for manufacturing a silicon carbide semiconductor device according to claim 10, wherein

a distance between a side surface of the first region and a side surface of the second region in a direction in parallel to the second main surface is not smaller than 0.6 μ

m and not greater than 1.5 μ

m.

21. (canceled)

22. (canceled)