LOW-LOSS AND FAST ACTING SOLID-STATE BREAKER

• US 20170141558A1
• Filed: 11/08/2016
• Published: 05/18/2017
• Est. Priority Date: 11/13/2015
• Status: Active Grant

• Current Assignee: Excelitas Technologies Corporation (Excelitas Technologies Holdings LLC)
• Original Assignee: Silicon Power Corporation
• Inventors: WALDRON, JOHN E., BRANDMIER, Kenneth, AZOTEA, James K.
• Granted Patent: US 10,193,322 B2
• Time in Patent Office: Days
• CPC Class Codes: H02H 3/027 with automatic disconnection after a predetermined time H02H3/033, H02H3/06 take precedence ; timing in overcurrent protection circuits H02H3/093; in undervoltage protection circuits H02H3/247; staggered disconnection H02H7/30
• CPC Class Codes: H02H 3/033 with several disconnections in a preferential order, e.g. following priority of the users, load repartitionH02H3/06 takes precedence
• CPC Class Codes: H02H 3/08 responsive to excess current responsive to abnormal temperature caused by excess current H02H5/04
• CPC Class Codes: H02H 3/20 responsive to excess voltage
• CPC Class Codes: H02H 3/44 responsive to the rate of change of electrical quantities
• CPC Class Codes: H03K 17/0416 by measures taken in the output circuit
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Abstract

A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO'"'"'s minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF. Alternatively, the circuit is used as an inverter switch, where at the command to turn ON is supplied, the at least one IGBT is turned ON, followed by the at least one SGTO. When commanded to turn OFF the at least one SGTO is turned OFF followed by the at least one IGBT. This alternative configuration allows the robust, controllable switching speeds of IGBTs and the superior conduction efficiency of SGTOs. The two configurations mentioned above utilize a wide range of SGTO performance, thus the ability to control the SGTOs turn-off speed by reducing its minority carrier lifetime after the device is processed is of large importance. The efficiency of all uses of the circuit can be optimized with the judicious selection of SGTO minority carrier lifetime and the ratio of active area between the SGTO and IGBT devices. In all cases there is a balance between the time the circuit can achieve hard turn-off without current commutation, the conduction efficiency of the circuit and the maximum amount of controllable current. In all cases both the conduction efficiency of the circuit is higher than an IGBT-only based circuit, and the switching performance is higher than a GTO-only based circuit.

Claims

1. A circuit for isolating a load from a source, the circuit comprising:

at least one insulated-gate bipolar transistor (IGBT); and

at least one gate turn-off thyristor (GTO) connected in parallel with the insulated-gate bipolar transistor.

2. The circuit of claim 1, wherein

the at least one IGBT comprises a collector, a gate, and an emitter, and

the at least one GTO comprises an anode, a gate, and a cathode,

wherein the collector of the at least one IGBT is connected to the anode of the at least one GTO, and

wherein the emitter of the at least one IGBT is connected to the cathode of the at least one GTO.

3. The circuit of claim 1, wherein the at least one GTO is a super GTO.

4. The circuit of claim 1,

wherein when no fault condition exists the at least one GTO is configured to be ON to couple the load to the source, and

wherein when a fault condition exists;

the at least one IGBT is configured to turn on;

the at least one GTO is configured to turn OFF after the at least one IGBT turns on; and

the at least one IGBT is configured to turn OFF a predetermined amount of time after the at least one GTO turns OFF.

5. A circuit comprising:

a source;

a load; and

an isolation circuit disposed between the source and the load, the isolation circuit comprising;

at least one insulated-gate bipolar transistor (IGBT); and

at least one gate turn-off thyristor (GTO) connected in parallel with the insulated-gate bipolar transistor.

6. The circuit of claim 5,

wherein when no fault condition exists the at least one GTO is configured to be ON to couple the load to the source, and

wherein when a fault condition exists:

the at least one IGBT is configured to turn on;

the at least one GTO is configured to turn OFF after the at least one IGBT turns on; and

the at least one IGBT is configured to turn OFF a predetermined amount of time alter the at least one GTO turns OFF.

7. The circuit of claim 6, wherein the predetermined amount of lime is based on the operating temperature of the at least one GTO.

8. The circuit of claim 6, wherein the predetermined amount of time is further based on a rate of change of an expected fault current through the at least one IGBT.

9. The circuit of claim 6, wherein the predetermined amount of time is based on a rate of change of an expected fault current through the at least one IGBT.

10. The circuit of claim 5, further comprising a controller configured to detect when a fault condition exists and, when a fault conditions exists, to:

turn ON the at least one IGBT;

turn OFF the at least one GTO after turning ON the IGBT; and

turn OFF the at least one IGBT a predetermined amount of time after turning OFF the at least one GTO.

11. The circuit of claim 5, wherein

the at least one IGBT comprises a collector, a gate, and an emitter, and

the at least one GTO comprises an anode, a gate, and a cathode,

wherein the collector of the at least one IGBT is connected to the anode of the at least one GTO, and

wherein the emitter of the at least one IGBT is connected to the cathode of the at least one GTO.

12. The circuit of claim 11, further comprising a controller connected to the gate of the at least one IGBT and to the gate of the at least one GTO.

13. The circuit of claim 12, wherein the controller is configured when no fault condition exists to supply a signal to the gate of the at least one GTO and when a fault conditions exists to:

supply a signal to the gate of the at least one IGBT to turn ON the at least one IGBT;

remove the signal from the gate of the at least one GTO to turn OFF the at least one GTO after turning ON the IGBT; and

remove the signal from the gate of the at least one IGBT to turn OFF the at least one IGBT a predetermined amount of time alter turning OFF the at least one GTO.

14. The circuit of claim 13, wherein the predetermined amount of time is based on the operating temperature of the at least one GTO.

15. The circuit of claim 14, wherein the predetermined amount of time is further based on a rate of change of an expected fault current through the at least one IGBT.

16. The circuit of claim 13, wherein the predetermined amount of time is based on a rate of change of an expected fault current through the at least one IGBT.

17. The circuit of claim 5, further comprising a reactance in series with the isolation circuit.

18. A circuit assembly comprising:

a source having a first end and a second end;

a load having a first end and a second end opposite the first end;

a first circuit coupled to the first end of said source and the first end of said load; and

a second circuit coupled to the second end of said source and the second end of said load, whereby when said first circuit and said second circuit are ON, a first current flows through said load.

19. The circuit assembly of claim 18, further comprising a third circuit coupled to the first end of said source and the second end of said load, and a fourth circuit coupled to the second end of said source and the first end of said load, whereby when said third circuit and said fourth circuit are ON, a second current flows through said load.

20. The circuit assembly of claim 19, wherein said first current flows in a first direction through said load and said second current flows in a second direction opposite the first direction through said load.

21. The circuit assembly of claim 18, wherein said first circuit, second circuit, third circuit and fourth circuit comprise an H-bridge assembly.

22. The circuit assembly of claim 18, further comprising a first diode coupled in parallel with said first circuit and a second diode coupled in parallel with said second circuit.

23. The circuit assembly of claim 22, further comprising a third diode coupled in parallel with said third circuit and a fourth diode coupled in parallel with said fourth circuit.

24. The circuit assembly of claim 18, further comprising a first controller connected to the first, circuit to turn the first circuit ON and OFF, and a second controller connected to the second circuit to turn the second circuit ON and OFF.

25. The circuit assembly of claim 24, further comprising a third controller connected to the third circuit to turn the third circuit ON and OFF, and a fourth controller connected to the fourth circuit to turn the fourth circuit ON and OFF.

26. The circuit assembly of claim 18, wherein said first, second, third and or fourth circuits comprise an insulated-gate bipolar transistor (IGBT) or a gate turn-off thyristor (GTO).

27. The circuit assembly of claim 26, wherein said first, second, third and/or fourth circuits comprise at least one IGBT and at least one GTO connected in parallel with the IGBT.