Power Amplifier and Gain Switching Circuit Thereof

• US 20170141749A1
• Filed: 01/29/2017
• Published: 05/18/2017
• Est. Priority Date: 12/30/2013
• Status: Active Grant

• Current Assignee: Lansus Technologies Inc.
• Original Assignee: Lansus Technologies Inc.
• Inventors: ZHAO, Qian, ZHANG, Liyang, CHENG, Zhenjuan, TANG, Dongjie, LONG, Hua
• Granted Patent: US 9,887,679 B2
• Time in Patent Office: Days
• CPC Class Codes: H03F 1/0211 with control of the supply voltage or current
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/111 the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/36 the amplifier comprising means for increasing the bandwidth
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/405 the output amplifying stage of an amplifier comprising more than three power stages
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/462 the current being sensed
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04

Abstract

A power amplifier gain switching circuit includes: a gain controller configured to receive an external input signal, output a first input signal, receive an external drive signal, and output a control signal based on the drive signal; an amplifier including: a bias input terminal configured to receive an external bias voltage; a signal input terminal configured to receive the first input signal; a control terminal configured to receive the control signal; and an output terminal configured to output an output signal with a gain; wherein the amplifier is configured to switch a gain factor of the output signal based on the control signal.

Claims

1. A power amplifier gain switching circuit, comprising:

a gain controller configured to receive an external input signal, output a first input signal, receive an external drive signal, and output a control signal based on the drive signal;

an amplifier including;

a bias input terminal configured to receive an external bias voltage;

a signal input terminal configured to receive the first input signal;

a control terminal configured to receive the control signal; and

an output terminal configured to output an output signal with a gain;

wherein the amplifier is configured to switch a gain factor of the output signal based on the control signal.

2. The power amplifier gain switching circuit of claim 1, wherein:

the gain controller comprises a first DC-blocking capacitor, a first resistor, a first power transistor, a second power transistor, a second resistor, and a third resistor,

one terminal of the first DC-blocking capacitor is configured to receive the input signal, and another terminal of the first DC-blocking capacitor is configured to output the first input signal through the first resistor;

the first and second power transistors have bases configured to receive the drive signal, and emitters grounded;

a collector of the first power transistor is connected in series with the first resistor through the second resistor, and a collector of the second power transistor is connected with the control terminal through the third resistor.

3. The power amplifier gain switching circuit of claim 2, wherein the gain controller comprises a plurality of gain control units connected in parallel.

4. The power amplifier gain switching circuit of claim 3, wherein first DC-blocking capacitors in the gain control units are combined into one DC-blocking capacitor, and first resistors in the gain control units are combined into one resistor.

5. The power amplifier gain switching circuit of claim 1, wherein:

the drive signal comprises a high level and a low level.

if the gain controller receives the low level, the gain controller will stop and not output the control signal; and

if the gain controller receives the high level, the gain controller will turn on and output the control signal, thereby reducing the gain factor of the output signal.

6. The power amplifier gain switching circuit of claim 1, wherein:

the gain controller is configured to DC-block and pull down the external input signal to generate the first input signal.

7. The power amplifier gain switching circuit of claim 1, wherein:

the amplifier comprises a first amplifier and a second amplifier;

the first amplifier includes;

a first bias input terminal configured to receive the external bias voltage;

a first signal input terminal configured to receive the first input signal;

a first output terminal configured to output a primary output signal gained for a first time, and

the control terminal configured to receive the control signal; and

the second amplifier includes;

a second bias input terminal configured to receive the bias voltage;

a second signal input terminal configured to receive the primary output signal; and

a second output terminal configured to output the output signal gained for a second time.

8. The power amplifier gain switching circuit of claim 7, wherein:

the first amplifier comprises a third power transistor, a fourth power transistor, a second DC-blocking capacitor, a fourth resistor, and a first inductor;

a base of the third power transistor is configured as the first bias input terminal;

a collector of the third power transistor is connected to a first power supply;

an emitter of the third power transistor is connected to a base of the fourth power transistor through the fourth resistor;

a base of the fourth power transistor is configured as the control terminal;

a collector of the fourth power transistor is configured as the first output terminal and connected to one terminal of the first inductor;

another terminal of the first inductor is connected to a second power supply;

an emitter of the fourth power transistor grounded;

one terminal of the second DC-blocking capacitor is configured as the first signal input terminal; and

another terminal of the second DC-blocking capacitor is connected to a base of the fourth power transistor.

9. The power amplifier gain switching circuit of claim 7, wherein:

the second amplifier comprises a fifth power transistor, a sixth power transistor, a third DC-blocking capacitor, a fifth resistor, and a second inductor;

a base of the fifth power transistor is configured as the first bias input terminal;

a collector of the fifth power transistor is connected to the first power supply;

an emitter of the fifth power transistor is connected to a base of the sixth power transistor through the fifth resistor;

a collector of the sixth power transistor is configured as the output terminal of the amplifier and connected to one terminal of the first inductor;

another terminal of the second inductor is connected to a third power supply;

an emitter of the sixth power transistor grounded;

one terminal of the third DC-blocking capacitor is configured as the second signal input terminal and connected to the collector of the fourth power transistor; and

another terminal of the third DC-blocking capacitor is connected to a base of the sixth power transistor.

10. A power amplifier gain switching circuit, comprising:

a gain controller configured to receive an external input signal, output a first input signal, receive an external drive signal, and output a control signal based on the drive signal;

wherein the gain controller comprises a plurality of gain control units connected in parallel;

an amplifier including;

a bias input terminal configured to receive an external bias voltage;

a signal input terminal configured to receive the first input signal;

a control terminal configured to receive the control signal; and

an output terminal configured to output an output signal with a gain;

wherein the amplifier is configured to switch a gain factor of the output signal based on the control signal;

each gain control unit comprises a first DC-blocking capacitor, a first resistor, a first power transistor, a second power transistor, a second resistor, and a third resistor,

one terminal of the first DC-blocking capacitor is configured to receive the input signal, and another terminal of the first DC-blocking capacitor is configured to output the first input signal through the first resistor;

the first and second power transistors have bases configured to receive the drive signal, and emitters grounded;

a collector of the first power transistor is connected in series with the first resistor through the second resistor, and a collector of the second power transistor is connected with the control terminal through the third resistor.

11. The power amplifier gain switching circuit of claim 10, wherein first DC-blocking capacitors in the gain control units are combined into one DC-blocking capacitor, and first resistors in the gain control units are combined into one resistor.

12. The power amplifier gain switching circuit of claim 11, wherein:

the drive signal comprises a high level and a low level.

if the gain control unit receives the low level, the gain control unit will stop and not output the control signal; and

if the gain control unit receives the high level, the gain control unit will turn on and output the control signal, thereby reducing the gain factor of the output signal.

13. The power amplifier gain switching circuit of claim 10, wherein:

the gain controller is configured to DC-block and pull down the external input signal to generate the first input signal.

14. The power amplifier gain switching circuit of claim 10, wherein:

the amplifier comprises a first amplifier and a second amplifier;

the first amplifier includes;

a first bias input terminal configured to receive the external bias voltage;

a first signal input terminal configured to receive the first input signal;

a first output terminal configured to output a primary output signal gained for a first time, and

the control terminal configured to receive the control signal; and

the second amplifier includes;

a second bias input terminal configured to receive the bias voltage;

a second signal input terminal configured to receive the primary output signal; and

a second output terminal configured to output the output signal gained for a second time.

15. The power amplifier gain switching circuit of claim 14, wherein:

the first amplifier comprises a third power transistor, a fourth power transistor, a second DC-blocking capacitor, a fourth resistor, and a first inductor;

a base of the third power transistor is configured as the first bias input terminal;

a collector of the third power transistor is connected to a first power supply;

an emitter of the third power transistor is connected to a base of the fourth power transistor through the fourth resistor;

a base of the fourth power transistor is configured as the control terminal;

a collector of the fourth power transistor is configured as the first output terminal and connected to one terminal of the first inductor;

another terminal of the first inductor is connected to a second power supply;

an emitter of the fourth power transistor grounded;

one terminal of the second DC-blocking capacitor is configured as the first signal input terminal; and

another terminal of the second DC-blocking capacitor is connected to a base of the fourth power transistor.

16. The power amplifier gain switching circuit of claim 15, wherein:

the second amplifier comprises a fifth power transistor, a sixth power transistor, a third DC-blocking capacitor, a fifth resistor, and a second inductor;

a base of the fifth power transistor is configured as the first bias input terminal;

a collector of the fifth power transistor is connected to the first power supply;

an emitter of the fifth power transistor is connected to a base of the sixth power transistor through the fifth resistor;

a collector of the sixth power transistor is configured as the output terminal of the amplifier and connected to one terminal of the first inductor;

another terminal of the second inductor is connected to a third power supply;

an emitter of the sixth power transistor grounded;

one terminal of the third DC-blocking capacitor is configured as the second signal input terminal and connected to the collector of the fourth power transistor; and

another terminal of the third DC-blocking capacitor is connected to a base of the sixth power transistor.

17. A power amplifier comprising:

a bias voltage generating circuit configured to generate a bias voltage;

a drive signal generating circuit configured to generate a drive signal; and

a power amplifier gain switching circuit including;

a gain controller configured to receive an external input signal, output a first input signal, receive the drive signal, and output a control signal based on the drive signal;

an amplifier including;

a bias input terminal configured to receive the bias voltage;

a signal input terminal configured to receive the first input signal;

a control terminal configured to receive the control signal; and

an output terminal configured to output an output signal with a gain;

wherein the amplifier is configured to switch a gain factor of the output signal based on the control signal.

18. The power amplifier of claim 17, wherein:

the gain controller comprises a first DC-blocking capacitor, a first resistor, a first power transistor, a second power transistor, a second resistor, and a third resistor,

one terminal of the first DC-blocking capacitor is configured to receive the input signal, and another terminal of the first DC-blocking capacitor is configured to output the first input signal through the first resistor;

the first and second power transistors have bases configured to receive the drive signal, and emitters grounded;

a collector of the first power transistor is connected in series with the first resistor through the second resistor, and a collector of the second power transistor is connected with the control terminal through the third resistor.

19. The power amplifier of claim 18, wherein:

the gain controller comprises a plurality of gain control units connected in parallel;

first DC-blocking capacitors in the gain control units are combined into one DC-blocking capacitor; and

first resistors in the gain control units are combined into one resistor.

20. The power amplifier of claim 18, wherein:

the gain controller is configured to DC-block and pull down the external input signal to generate the first input signal.