NON-VOLATILE BUFFER FOR MEMORY OPERATIONS

• US 20170147207A1
• Filed: 11/20/2015
• Published: 05/25/2017
• Est. Priority Date: 11/20/2015
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Wang, Wei, Hansson, Andreas, Diestelhorst, Stephan, de Jong, lrenus Johannes
• Granted Patent: US 10,719,236 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 15/7853 including a ROM
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Subject matter disclosed herein may relate to buffers, and may relate more particularly to non-volatile buffers for memory operations.

Claims

1. An apparatus, comprising:

an on-chip memory controller to interface with an off-chip non-volatile memory device, wherein the on-chip memory controller to comprise a non-volatile buffer, to be formed from a non-volatile memory technology, to store one or more signals and/or states to comprise a memory operation to be received from a processor.

2. The apparatus of claim 1, wherein the memory operation to comprise a persistent memory operation.

3. The apparatus of claim 2, the on-chip memory controller to signal to the processor completion of the persistent memory operation prior to communicating the persistent memory operation to the off-chip non-volatile memory device.

4. The apparatus of claim 3, wherein the non-volatile buffer to maintain the persistent memory operation upon a removal of power, and wherein the memory controller to communicate the persistent memory operation to the off-chip non-volatile memory device at least in part in response to a restoration of power.

5. The apparatus of claim 1, wherein the non-volatile buffer to comprise one or more correlated electron switch devices.

6. The apparatus of claim 1, wherein the non-volatile buffer to represent a point of persistency substantially adjacent to the processor.

7. The apparatus of claim 1, wherein the memory operation to comprise a write operation.

8. A method, comprising:

storing, in a non-volatile buffer formed from a non-volatile memory technology, one or more signals and/or states comprising a memory operation communicated by a processor, wherein the memory operation is addressed to an off-chip non-volatile memory device; and

communicating to the processor a completion of the memory operation at least in part in response to the storing the one or more signals and/or states comprising the memory operation in the non-volatile buffer.

9. The method of claim 8, wherein the non-volatile buffer comprises a non-volatile buffer of an on-chip memory controller.

10. The method of claim 8, further comprising communicating the one or more signals and/or states comprising the memory operation from the non-volatile buffer to the off-chip non-volatile memory device at a point in time after the communicating to the processor the completion of the memory operation.

11. The method of claim 10, wherein the communicating the one or more signals and/or states comprising the memory operation from the non-volatile buffer to the off-chip non-volatile memory device at the point in time after the communicating to the processor the completion of the memory operation further comprises communicating the one or more signals and/or states comprising the memory operation from the non-volatile buffer to the off-chip non-volatile memory device at least in part in response to a removal and subsequent restoration of power.

12. The method of claim 8, wherein the storing the one or more signals and/or states comprising the memory operation in the non-volatile buffer comprises causing a transition in one or more correlated electron switches of a plurality of correlated electron switches of the non-volatile buffer from a first impedance state to a second impedance state.

13. The method of claim 12, wherein the causing the transition in the one or more correlated electron switches of the plurality of correlated electron switches of the non-volatile buffer from the first impedance state to the second impedance state comprises applying a programming voltage and/or current sufficient to achieve a set condition in the one or more correlated electron switches of the plurality of correlated electron switches of the non-volatile buffer, wherein the first impedance state comprises a higher impedance state and the second impedance state comprises a lower impedance state.

14. The method of claim 13, wherein the higher impedance state represents a binary value of “

0” and

lower impedance state represents a binary value of “

1”

.

15. The method of claim 8, wherein the memory operation comprises a persistent write operation, and wherein the non-volatile buffer represents a point of persistency substantially adjacent to the processor.

16. A system, comprising:

a non-volatile memory device;

a processor to execute a persistent memory operation directed to a memory location in the non-volatile memory device; and

a memory controller to obtain one or more signals and/or states to comprise the persistent memory operation from the processor, wherein the memory controller to comprise a non-volatile buffer to store the persistent memory operation.

17. The system of claim 16, wherein the non-volatile buffer to represent a point of persistency substantially adjacent to the processor.

18. The system of claim 17, wherein the processor and memory controller are located on a particular integrated circuit die, wherein the non-volatile memory device is not located on the particular integrated circuit die, and wherein the non-volatile buffer to comprise one or more correlated electron switch devices.

19. The system of claim 18, wherein the memory controller to signal to the processor completion of the persistent memory operation prior to the processor to communicate the persistent memory operation to the non-volatile memory device.

20. The system of claim 19, wherein the non-volatile buffer to maintain the persistent memory operation upon a removal of power from the memory controller, and wherein the memory controller to communicate the persistent memory operation to the non-volatile memory device at least in part in response to a restoration of power to the memory controller.