COMPUTATION ALONG A DATAPATH BETWEEN MEMORY BLOCKS

• US 20170147228A1
• Filed: 11/25/2015
• Published: 05/25/2017
• Est. Priority Date: 11/25/2015
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yudanov, Dmitri, Meswani, Mitesh R., Ignatowski, Michael, Roberts, David A., Jayasena, Nuwan, Blagodurov, Sergey
• Application Number:
  US14/952,517
• Publication Number:
  US 20170147228A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 2212/1024 Latency reduction

Abstract

A plurality of memory blocks are connected to a computation-enabled switch that provides data paths between the plurality of memory blocks. The computation-enabled switch performs one or more computations on data stored in one or more of the plurality of memory blocks during transfer of the data along one or more of the data paths between the plurality of memory blocks.

Claims

1. An apparatus, comprising:

a plurality of memory blocks; and

a computation-enabled switch that provides data paths between the plurality of memory blocks, and wherein the computation-enabled switch is to perform at least one computation on data stored in at least one of the plurality of memory blocks during transfer of the data along at least one data path between the plurality of memory blocks.

2. The apparatus of claim 1, wherein the computation-enabled switch is to perform at least one of swapping, redirecting, and routing the data along the at least one data path between the plurality of memory blocks.

3. The apparatus of claim 2, wherein the data is transferred along the at least one memory path between the plurality of memory blocks in at least one packet, and wherein the computation-enabled switch is to detect at least one tag associated with the at least one packet including the data and direct the at least one packet to a compute element in response to detecting the at least one tag.

4. The apparatus of claim 2, wherein the computation-enabled switch comprises:

a switch to swap, redirect, or route the data along the at least one data path between the plurality of memory blocks; and

a compute element to perform the at least one computation on the data as the data during transfer of the data along the at least one data path.

5. The apparatus of claim 4, wherein:

the computation-enabled switch comprises a plurality of buffers associated with the plurality of memory blocks, and

the plurality of buffers store data received from the plurality of memory blocks and store data received from the switch.

6. The apparatus of claim 2, wherein the computation-enabled switch comprises at least one multiplexer to swap, redirect, or route the data along the at least one data path between the plurality of memory blocks.

7. The apparatus of claim 2, wherein the computation-enabled switch comprises an on-chip switch network integrated with a compute element.

8. The apparatus of claim 1, wherein the plurality of memory blocks comprise:

at least one first memory block that operates according to a first memory access protocol; and

at least one second memory block that operates according to a second memory access protocol that is different than the first memory access protocol.

9. The apparatus of claim 1, further comprising:

a processor connected to the computation-enabled switch, wherein the processor is to;

receive data stored in at least one of the plurality of memory blocks from the computation-enabled switch; and

perform at least one operation on the received data, and

wherein the computation-enabled switch is to bypass the processor during transfer of the data along the at least one data path between the plurality of memory blocks.

10. A method, comprising:

receiving, at a computation-enabled switch, data stored in at least one of a plurality of memory blocks connected to the computation-enabled switch, wherein the computation-enabled switch provides data paths between the plurality of memory blocks;

transferring data along at least one data path between the plurality of memory blocks provided by the computation-enabled switch; and

performing, at the computation-enabled switch, at least one computation on the data as the data is transferred along the at least one data path.

11. The method of claim 10, wherein the data is transferred along the at least one memory path between the plurality of memory blocks in at least one packet, and further comprising:

detecting, at the computation-enabled switch, at least one tag in the at least one packet containing the data; and

directing the at least one packet to a compute element in response to detecting the at least one tag, wherein the compute element is to perform the at least one computation on the data.

12. The method of claim 10, further comprising:

performing, at the computation-enabled switch, at least one of swapping, redirecting, and routing the data along the at least one data path between the plurality of memory blocks.

13. The method of claim 10, further comprising:

bypassing a processor connected to the computation-enabled switch during transfer of the data along the at least one data path between the plurality of memory blocks.

14. An apparatus, comprising:

at least one processor core;

a plurality of memory blocks; and

an computation-enabled switch connected to the at least one processor core and the plurality of memory blocks, wherein the computation-enabled switch provides data paths between the plurality of memory blocks that bypass the at least one processor core, and wherein the computation-enabled switch is to perform at least one computation on data stored in at least one of the plurality of memory blocks during transfer of the data along at least one data path that bypasses the at least one processor core.

15. The apparatus of claim 14, further comprising:

at least one cache deployed between the at least one processor core and the computation-enabled switch, wherein the data paths provided by the computation-enabled switch between the plurality of memory blocks bypass the at least one cache.

16. The apparatus of claim 14, wherein the computation-enabled switch is to perform at least one of swapping, redirecting, and routing the data along the at least one data path between the plurality of memory blocks.

17. The apparatus of claim 16, wherein the data is transferred along the at least one memory path between the plurality of memory blocks in at least one packet, and wherein the computation-enabled switch is to detect at least one tag associated with the at least one packet including the data and direct the at least one packet to a compute element in response to detecting the tag.

18. The apparatus of claim 16, wherein the computation-enabled switch comprises a switch to perform at least one of swapping, redirecting or routing the data along the at least one data path between the plurality of memory blocks and a compute element to perform the at least one computation on the data during transfer of the data along the at least one data path.

19. The apparatus of claim 14, further comprising:

a plurality of memory controllers associated with the plurality of memory blocks.

20. The apparatus of claim 14, wherein the plurality of memory blocks comprise at least one first memory block that operates according to a first memory access protocol and at least one second memory block that operates according to a second memory access protocol that is different than the first memory access protocol.