FLASHWARE USAGE MITIGATION

• US 20170147238A1
• Filed: 11/24/2015
• Published: 05/25/2017
• Est. Priority Date: 11/24/2015
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Jindal, Rohit, Dumov, Leo
• Granted Patent: US 10,474,570 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, a memory control process of a device receives a plurality of program/erase (P/E) requests for a flash memory of the device. The memory control process then stores data associated with the plurality of P/E requests in a random access memory (RAM) of the device, and aggregates the plurality of P/E requests into a single P/E operation. The memory control process may then send the single P/E operation to the flash memory at a given interval to update the flash memory with the data stored in the RAM.

Claims

1. A method, comprising:

receiving, at a memory control process of a device, a plurality of program/erase (P/E) requests for a flash memory of the device;

storing, by the memory control process, data associated with the plurality of P/E requests in a random access memory (RAM) of the device;

aggregating, by the memory control process, the plurality of P/E requests into a single P/E operation; and

sending, from the memory control process, the single P/E operation to the flash memory at a given interval to update the flash memory with the data stored in the RAM.

2. The method as in claim 1, wherein the given interval is time-based.

3. The method as in claim 2, further comprising:

determining the time-based given interval based on one or more of a total size of the flash memory, an amount of the flash memory allocated to one or more applications generating the plurality of P/E requests, a type of the flash memory, and a projected lifetime of the flash memory.

4. The method as in claim 1, wherein the given interval is based on a number of the aggregated plurality of P/E requests.

5. The method as in claim 1, wherein the given interval is based on a size of the single P/E operation from the aggregated plurality of P/E requests.

6. The method as in claim 1, wherein the given interval is based on a particular application forcing a P/E operation to the flash memory.

7. The method as in claim 1, further comprising:

receiving, at the memory control process, a read request for the flash memory of the device; and

sending, from the memory control process, the read request to the flash memory.

8. The method as in claim 7, further comprising:

determining, in response to receiving the read request, if requested data of the read request corresponds to a more recent copy of the requested data stored in the RAM; and

if so, sending, from the memory control process, the read request to the RAM.

9. The method as in claim 1, wherein the device is a router.

10. The method as in claim 1, wherein a core operating system owns the flash memory, and wherein the memory control process is located within a hypervisor operating system that hosts applications in a virtual environment, the RAM being accessible directly to the hypervisor operating system, the memory control process configured to send the single P/E operation to the flash memory via an interface to the core operating system.

11. The method as in claim 1, further comprising:

dedicating a first portion of the flash memory to a core operating system; and

dedicating a second portion of the flash memory to applications executed by an operating system other than the core operating system, the second portion distinct from the first portion;

wherein aggregating the plurality of P/E requests and sending the single P/E operation is based on the dedicated first and second portions.

12. An apparatus, comprising:

a processor configured to execute one or more processes;

a flash memory;

a random access memory (RAM); and

an operating system configured to store a memory control process executable by the processor, the memory control process when executed operable to;

receive a plurality of program/erase (P/E) requests for the flash memory;

store data associated with the plurality of P/E requests in the RAM;

aggregate the plurality of P/E requests into a single P/E operation; and

send the single P/E operation to the flash memory at a given interval to update the flash memory with the data stored in the RAM.

13. The apparatus as in claim 12, wherein the given interval is time-based.

14. The apparatus as in claim 13, wherein the process when executed is further operable to:

determine the time-based given interval based on one or more of a total size of the flash memory, an amount of the flash memory allocated to one or more applications generating the plurality of P/E requests, a type of the flash memory, and a projected lifetime of the flash memory.

15. The apparatus as in claim 12, wherein the given interval is based on at least one of:

a number of the aggregated plurality of P/E requests, a size of the single P/E operation from the aggregated plurality of P/E requests, and a particular application forcing a P/E operation to the flash memory.

16. The apparatus as in claim 12, wherein the process when executed is further operable to:

receive a read request for the flash memory of the device; and

determine, in response to receiving the read request, if requested data of the read request corresponds to a more recent copy of the requested data stored in the RAM;

if so, send the read request to the RAM; and

if not, send the read request to the flash memory.

17. The apparatus as in claim 12, wherein the apparatus is a router.

18. The apparatus as in claim 12, wherein a core operating system of the apparatus owns the flash memory, and wherein the memory control process is located within a hypervisor operating system of the apparatus that hosts applications in a virtual environment, the RAM being accessible directly to the hypervisor operating system, the memory control s process configured to send the single P/E operation to the flash memory via an interface to the core operating system.

19. The apparatus as in claim 12, wherein the process when executed is further operable to:

dedicate a first portion of the flash memory to a core operating system; and

dedicate a second portion of the flash memory to applications executed by an operating system other than the core operating system, the second portion distinct from the first portion;

wherein aggregating the plurality of P/E requests and sending the single P/E operation is based on the dedicated first and second portions.

20. A tangible, non-transitory, computer-readable media having software encoded thereon, the software when executed by a processor operable to:

receive a plurality of program/erase (P/E) requests for a flash memory of a device;

store data associated with the plurality of P/E requests in a random access memory (RAM) of the device;

aggregate the plurality of P/E requests into a single P/E operation; and

send the single P/E operation to the flash memory at a given interval to update the flash memory with the data stored in the RAM.