VERIFIED COMPILATION OF REVERSIBLE CIRCUITS
First Claim
1. A computer-implemented method, comprising:
- by a verification tool adapted to perform formal verification of a reversible circuit compiler and implemented by one or more computing devices;
verifying operation of the reversible circuit compiler, the reversible circuit compiler being configured to generate a reversible circuit from a high-level program description of the reversible circuit,wherein the verifying includes verifying that an intermediate representation of the reversible circuit that is generated by the reversible circuit compiler satisfies one or more verification criteria relative to a higher-level intermediate representation of the reversible circuit that is also generated by the reversible circuit compiler.
1 Assignment
0 Petitions
Accused Products
Abstract
The generation of reversible circuits from high-level code is desirable in a variety of application domains, including low-power electronics and quantum computing. However, little effort has been spent on verifying the correctness of the results, an issue of particular importance in quantum computing where such circuits are run on all inputs simultaneously. Disclosed herein are example reversible circuit compilers as well as tools and techniques for verifying the compilers. Example compilers disclosed herein compile a high-level language into combinational reversible circuits having a reduced number of ancillary bits (ancilla bits) and further having provably clean temporary values.
41 Citations
20 Claims
-
1. A computer-implemented method, comprising:
by a verification tool adapted to perform formal verification of a reversible circuit compiler and implemented by one or more computing devices; verifying operation of the reversible circuit compiler, the reversible circuit compiler being configured to generate a reversible circuit from a high-level program description of the reversible circuit, wherein the verifying includes verifying that an intermediate representation of the reversible circuit that is generated by the reversible circuit compiler satisfies one or more verification criteria relative to a higher-level intermediate representation of the reversible circuit that is also generated by the reversible circuit compiler. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
8. A system, comprising:
-
a processor; and at least one memory coupled to the processor and having stored thereon processor-executable instructions for implementing a verification process for a reversible circuit compiler, the reversible circuit compiler being configured to compile a behavioral description of a reversible circuit into a reversible gate set implementable in a target quantum circuit architecture, the compiler verification process comprising verifying that all ancilla bits that are allocated during reversible circuit compilation are returned to a clean state by the reversible gate set produced by the reversible circuit compiler. - View Dependent Claims (9)
-
-
10. A reversible circuit compilation system, comprising:
- a memory; and
a reversible circuit compiler, the reversible circuit compiler being configured to;
input, into the memory, a program describing a desired computation to be performed in a target reversible circuit architecture using bits, transform the program into a reversible circuit description specifying one or more reversible gates that use the bits to achieve the desired computation, and store, in the memory, the reversible circuit description, the reversible circuit compiler being further configured to, as part of the transformation of the program into the reversible circuit description;
apply one or more ancilla-reducing techniques to reduce the number of ancillas used by the reversible circuit description. - View Dependent Claims (11, 12, 13, 14, 15)
- a memory; and
- 16. A computer-implemented method, comprising, with a reversible circuit compiler, generating an output reversible circuit from a high-level program, the reversible circuit compiler being verified at all levels of intermediate internal representation.
Specification