BINARY PATTERNING FOR THREE-DIMENSIONAL MEMORY FORMATION

• US 20170147730A1
• Filed: 11/23/2015
• Published: 05/25/2017
• Est. Priority Date: 11/23/2015
• Status: Abandoned Application

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Shappir, Assaf
• Application Number:
  US14/948,407
• Publication Number:
  US 20170147730A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A method for designing a patterning process for a three-dimensional (3D) memory includes defining a target 3D structure of the 3D memory, to be applied in a periodic structure of layers on a substrate. The target 3D structure is converted into a sequence of multiple steps, each step specifying a respective pattern to be removed and a respective number of the layers to be removed from the periodic structure under the respective pattern. The sequence of steps is sent to one or more manufacturing tools.

Claims

1. A method for designing a patterning process for a three-dimensional (3D) memory, the method comprising:

defining a target 3D structure of the 3D memory, to be applied in a periodic structure of layers on a substrate;

converting the target 3D structure into a sequence of multiple steps, each step specifying a respective pattern to be removed and a respective number of the layers to be removed from the periodic structure under the respective pattern; and

sending the sequence of steps to one or more manufacturing tools.

2. The method according to claim 1, wherein the periodic structure comprises two or more layers, and wherein at least two of the layers of the periodic structure differ in material composition.

3. The method according to claim 1, wherein the periodic structure comprises two or more layers, and wherein at least two of the layers of the periodic structure differ in material thickness.

4. The method according to claim 1, wherein at least two of the steps in the sequence specify different respective patterns.

5. The method according to claim 1, wherein at least two of the steps in the sequence specify different respective numbers of the layers to be removed.

6. The method according to claim 1, wherein defining the target 3D structure further comprises defining a reference target 3D structure having a respective reference sequence of multiple steps designed for producing the reference target 3D structure, and wherein converting the target 3D structure comprises changing one or more properties of the steps of the reference sequence.

7. The method according to claim 6, wherein changing the one or more properties comprises at least one of reordering the steps in the reference sequence, modifying the pattern to be removed in at least one step in the reference sequence, and changing the number of the layers to be removed in at least one step in the reference sequence.

8. The method according to claim 1, wherein the layers of the periodic structure implement multiple memory arrays, wherein the target 3D structure comprises a staircase structure comprising multiple stair steps, and wherein at least one of the stair steps comprises at least one electrical contact, which is configured to connect between a respective memory array and a peripheral circuit.

9. The method according to claim 1, wherein the numbers of the layers to be removed form a sequence of powers of two.

10. A system for designing a patterning process for a three-dimensional (3D) memory, the system comprising:

an interface, which is configured to exchange information with one or more manufacturing tools; and

a processor, which is configured to define a target 3D structure of the 3D memory, to be applied in a periodic structure of layers on a substrate, to convert the target 3D structure into a sequence of multiple steps, each step specifying a respective pattern to be removed and a respective number of the layers to be removed from the periodic structure under the respective pattern, and to send, via the interface, the sequence of steps to the one or more manufacturing tools.

11. The system according to claim 10, wherein the periodic structure comprises two or more layers, and wherein at least two of the layers of the periodic structure differ in material composition.

12. The system according to claim 10, wherein the periodic structure comprises two or more layers, and wherein at least two of the layers of the periodic structure differ in material thickness.

13. The system according to claim 10, wherein at least two of the steps in the sequence specify different respective patterns.

14. The system according to claim 10, wherein at least two of the steps in the sequence specify different respective numbers of the layers to be removed.

15. The system according to claim 10, wherein the target 3D structure further comprises a reference target 3D structure having a respective reference sequence of multiple steps designed for producing the reference target 3D structure, and wherein the processor is configured to convert the reference target 3D structure by changing one or more properties of the steps of the reference sequence.

16. The system according to claim 15, wherein the processor is configured to change the properties by performing at least one of reordering the steps in the reference sequence, modifying the pattern to be removed in at least one step in the reference sequence, and changing the number of the layers to be removed in at least one step in the reference sequence.

17. The system according to claim 10, wherein the layers of the periodic structure implement multiple memory arrays, wherein the target 3D structure comprises a staircase structure comprising multiple stair steps, and wherein at least one of the stair steps comprises at least one electrical contact, which is configured to connect between a respective memory array and a peripheral circuit.

18. The system according to claim 10, wherein the numbers of the layers to be removed form a sequence of powers of two.

19. A non-transitory computer-readable medium including instructions that, when executed by one or more processors, cause the one or more processors to perform a method for designing a patterning process for a three-dimensional (3D) device, comprising:

defining a target 3D structure of the 3D device, to be applied in a periodic structure of layers on a substrate;

converting the target 3D structure into a sequence of multiple steps, each step specifying a respective pattern to be removed and a respective number of the layers to be removed from the periodic structure under the respective pattern; and

sending the sequence of steps to one or more manufacturing tools.

20. The non-transitory computer-readable medium of claim 19, wherein the 3D device comprises a 3D memory.